{"block":{"name":"chip","variant":null,"commit":"cbf0611ad746e9d6c7ba45219b8e4e9894cd04ab","commit_short":"cbf0611","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/cbf0611ad746e9d6c7ba45219b8e4e9894cd04ab","revision_info":"GitHub Revision: [`cbf0611`](https://github.com/lowrisc/opentitan/tree/cbf0611ad746e9d6c7ba45219b8e4e9894cd04ab)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-05-26T15:30:30Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/top_earlgrey/data/chip_testplan.html","stages":{"unmapped":{"testpoints":{"Unmapped":{"tests":{"chip_csr_bit_bash":{"max_time":332.26,"sim_time":4467.4538919999995,"passed":1,"total":1,"percent":100.0},"chip_csr_aliasing":{"max_time":5104.83,"sim_time":35835.918770000004,"passed":1,"total":1,"percent":100.0},"chip_same_csr_outstanding":{"max_time":2616.1,"sim_time":29673.930612,"passed":1,"total":1,"percent":100.0},"chip_sw_example_flash":{"max_time":104.04,"sim_time":2733.76388,"passed":1,"total":1,"percent":100.0},"chip_sw_example_rom":{"max_time":65.77,"sim_time":2376.7781299999997,"passed":1,"total":1,"percent":100.0},"chip_sw_example_manufacturer":{"max_time":121.09999999999998,"sim_time":2676.840279,"passed":1,"total":1,"percent":100.0},"chip_sw_example_concurrency":{"max_time":158.37,"sim_time":2450.67497,"passed":1,"total":1,"percent":100.0},"chip_sival_flash_info_access":{"max_time":202.87,"sim_time":3609.88528,"passed":1,"total":1,"percent":100.0},"chip_sw_all_escalation_resets":{"max_time":199.48,"sim_time":3216.01818,"passed":0,"total":1,"percent":0.0},"chip_sw_rstmgr_rst_cnsty_escalation":{"max_time":19.65,"sim_time":10.320001,"passed":0,"total":1,"percent":0.0},"chip_sw_data_integrity_escalation":{"max_time":428.53,"sim_time":5481.316599999999,"passed":1,"total":1,"percent":100.0},"chip_sw_sleep_pin_mio_dio_val":{"max_time":208.18,"sim_time":3319.296609,"passed":1,"total":1,"percent":100.0},"chip_sw_sleep_pin_wake":{"max_time":208.23,"sim_time":3862.3390440000003,"passed":1,"total":1,"percent":100.0},"chip_sw_sleep_pin_retention":{"max_time":198.02,"sim_time":3260.458099,"passed":1,"total":1,"percent":100.0},"chip_sw_sleep_pwm_pulses":{"max_time":824.47,"sim_time":8669.491404999999,"passed":1,"total":1,"percent":100.0},"chip_sw_pattgen_ios":{"max_time":139.15,"sim_time":3328.1329,"passed":1,"total":1,"percent":100.0},"chip_sw_uart_tx_rx":{"max_time":361.94,"sim_time":4570.900028,"passed":1,"total":1,"percent":100.0},"chip_sw_uart_tx_rx_idx1":{"max_time":394.09,"sim_time":4943.22758,"passed":1,"total":1,"percent":100.0},"chip_sw_uart_tx_rx_idx2":{"max_time":425.81,"sim_time":5027.920014,"passed":1,"total":1,"percent":100.0},"chip_sw_uart_tx_rx_idx3":{"max_time":349.04,"sim_time":4136.413848,"passed":1,"total":1,"percent":100.0},"chip_sw_uart_tx_rx_bootstrap":{"max_time":7889.18,"sim_time":63821.283355,"passed":1,"total":1,"percent":100.0},"chip_sw_usbdev_vbus":{"max_time":185.73,"sim_time":2778.2131600000002,"passed":1,"total":1,"percent":100.0},"chip_sw_usbdev_dpi":{"max_time":1881.22,"sim_time":12163.495872,"passed":1,"total":1,"percent":100.0},"chip_sw_usbdev_pullup":{"max_time":163.44,"sim_time":2906.5425950000003,"passed":1,"total":1,"percent":100.0},"chip_sw_usbdev_aon_pullup":{"max_time":256.69,"sim_time":3627.347784,"passed":1,"total":1,"percent":100.0},"chip_sw_usbdev_setuprx":{"max_time":314.75,"sim_time":3576.586682,"passed":1,"total":1,"percent":100.0},"chip_sw_usbdev_config_host":{"max_time":1017.5499999999998,"sim_time":8751.72241,"passed":1,"total":1,"percent":100.0},"chip_sw_usbdev_pincfg":{"max_time":5540.27,"sim_time":31688.268328000002,"passed":1,"total":1,"percent":100.0},"chip_sw_usbdev_stream":{"max_time":2980.07,"sim_time":18442.931856,"passed":1,"total":1,"percent":100.0},"chip_sw_usbdev_toggle_restore":{"max_time":168.68,"sim_time":3184.364088,"passed":1,"total":1,"percent":100.0},"chip_sw_inject_scramble_seed":{"max_time":8055.640000000001,"sim_time":57851.269983000006,"passed":1,"total":1,"percent":100.0},"chip_sw_exit_test_unlocked_bootstrap":{"max_time":7110.24,"sim_time":55138.088083999995,"passed":1,"total":1,"percent":100.0},"chip_sw_uart_rand_baudrate":{"max_time":1097.82,"sim_time":8534.362798,"passed":1,"total":1,"percent":100.0},"chip_sw_uart_tx_rx_alt_clk_freq":{"max_time":313.73,"sim_time":4024.838074,"passed":1,"total":1,"percent":100.0},"chip_sw_uart_tx_rx_alt_clk_freq_low_speed":{"max_time":1054.42,"sim_time":13705.331978,"passed":1,"total":1,"percent":100.0},"chip_sw_i2c_host_tx_rx":{"max_time":509.12,"sim_time":5700.077625,"passed":1,"total":1,"percent":100.0},"chip_sw_i2c_host_tx_rx_idx1":{"max_time":344.78,"sim_time":4326.754048000001,"passed":1,"total":1,"percent":100.0},"chip_sw_i2c_host_tx_rx_idx2":{"max_time":470.2,"sim_time":5919.537971,"passed":1,"total":1,"percent":100.0},"chip_sw_i2c_device_tx_rx":{"max_time":292.98,"sim_time":4318.442268,"passed":1,"total":1,"percent":100.0},"chip_sw_spi_device_tpm":{"max_time":218.32,"sim_time":3730.7468879999997,"passed":1,"total":1,"percent":100.0},"chip_sw_spi_host_tx_rx":{"max_time":143.82,"sim_time":2329.920646,"passed":1,"total":1,"percent":100.0},"chip_sw_spi_device_pinmux_sleep_retention":{"max_time":237.41,"sim_time":4360.9924519999995,"passed":1,"total":1,"percent":100.0},"chip_sw_spi_device_pass_through":{"max_time":263.52,"sim_time":3782.196357,"passed":1,"total":1,"percent":100.0},"chip_sw_spi_device_pass_through_collision":{"max_time":226.09,"sim_time":3566.54214,"passed":0,"total":1,"percent":0.0},"chip_sw_gpio":{"max_time":270.44,"sim_time":3729.149183,"passed":1,"total":1,"percent":100.0},"chip_sw_flash_ctrl_ops":{"max_time":396.87,"sim_time":4354.1761799999995,"passed":1,"total":1,"percent":100.0},"chip_sw_flash_ctrl_ops_jitter_en":{"max_time":377.69,"sim_time":4473.506709,"passed":1,"total":1,"percent":100.0},"chip_sw_flash_ctrl_lc_rw_en":{"max_time":137.34,"sim_time":3279.309427,"passed":0,"total":1,"percent":0.0},"chip_sw_flash_ctrl_access":{"max_time":575.36,"sim_time":5577.829559999999,"passed":1,"total":1,"percent":100.0},"chip_sw_flash_ctrl_access_jitter_en":{"max_time":602.74,"sim_time":5494.198255,"passed":1,"total":1,"percent":100.0},"chip_sw_flash_ctrl_idle_low_power":{"max_time":246.41,"sim_time":3466.200671,"passed":1,"total":1,"percent":100.0},"chip_sw_flash_init":{"max_time":1039.64,"sim_time":22286.592712,"passed":1,"total":1,"percent":100.0},"chip_sw_flash_rma_unlocked":{"max_time":3673.66,"sim_time":44397.80519,"passed":1,"total":1,"percent":100.0},"chip_sw_flash_ctrl_clock_freqs":{"max_time":566.76,"sim_time":5571.846226,"passed":1,"total":1,"percent":100.0},"chip_sw_kmac_entropy":{"max_time":1161.57,"sim_time":8307.753074,"passed":1,"total":1,"percent":100.0},"chip_sw_lc_ctrl_otp_hw_cfg0":{"max_time":201.4,"sim_time":3431.758548,"passed":1,"total":1,"percent":100.0},"chip_sw_otp_ctrl_lc_signals_test_unlocked0":{"max_time":203.15,"sim_time":3624.25719,"passed":1,"total":1,"percent":100.0},"chip_sw_otp_ctrl_lc_signals_dev":{"max_time":679.88,"sim_time":8821.63118,"passed":1,"total":1,"percent":100.0},"chip_sw_otp_ctrl_lc_signals_prod":{"max_time":474.34,"sim_time":5054.184422,"passed":1,"total":1,"percent":100.0},"chip_sw_otp_ctrl_lc_signals_rma":{"max_time":411.1,"sim_time":5278.721192,"passed":0,"total":1,"percent":0.0},"chip_sw_otp_ctrl_vendor_test_csr_access":{"max_time":126.74000000000001,"sim_time":2358.372585,"passed":1,"total":1,"percent":100.0},"chip_sw_otp_ctrl_escalation":{"max_time":174.64,"sim_time":3368.2016320000002,"passed":0,"total":1,"percent":0.0},"chip_sw_otp_ctrl_dai_lock":{"max_time":887.87,"sim_time":7610.892888,"passed":1,"total":1,"percent":100.0},"chip_sw_otp_ctrl_rot_auth_config":{"max_time":5.54,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"chip_sw_otp_ctrl_ecc_error_vendor_test":{"max_time":176.99,"sim_time":3332.811809,"passed":1,"total":1,"percent":100.0},"chip_sw_otp_ctrl_descrambling":{"max_time":249.74,"sim_time":3483.323444,"passed":1,"total":1,"percent":100.0},"chip_sw_lc_ctrl_transition":{"max_time":377.53,"sim_time":7781.528004,"passed":1,"total":1,"percent":100.0},"chip_sw_lc_ctrl_rma_to_scrap":{"max_time":127.53999999999999,"sim_time":3278.703295,"passed":1,"total":1,"percent":100.0},"chip_sw_lc_ctrl_raw_to_scrap":{"max_time":91.93,"sim_time":3827.332411,"passed":1,"total":1,"percent":100.0},"chip_sw_lc_ctrl_test_locked0_to_scrap":{"max_time":82.78,"sim_time":2782.187782,"passed":1,"total":1,"percent":100.0},"chip_sw_lc_ctrl_rand_to_scrap":{"max_time":102.47,"sim_time":3566.558951,"passed":1,"total":1,"percent":100.0},"chip_sw_lc_walkthrough_dev":{"max_time":832.08,"sim_time":26374.713656,"passed":0,"total":1,"percent":0.0},"chip_sw_lc_walkthrough_prod":{"max_time":620.57,"sim_time":7616.632570000001,"passed":0,"total":1,"percent":0.0},"chip_sw_lc_walkthrough_prodend":{"max_time":533.52,"sim_time":9317.100505,"passed":1,"total":1,"percent":100.0},"chip_sw_lc_ctrl_volatile_raw_unlock":{"max_time":919.26,"sim_time":26888.532084,"passed":0,"total":1,"percent":0.0},"chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz":{"max_time":63.17999999999999,"sim_time":2318.260779,"passed":1,"total":1,"percent":100.0},"chip_sw_lc_walkthrough_rma":{"max_time":374.78,"sim_time":7246.608434000001,"passed":0,"total":1,"percent":0.0},"chip_sw_lc_walkthrough_testunlocks":{"max_time":2053.02,"sim_time":38872.525200000004,"passed":1,"total":1,"percent":100.0},"chip_sw_rstmgr_sw_req":{"max_time":299.68,"sim_time":4726.05906,"passed":1,"total":1,"percent":100.0},"chip_sw_rstmgr_sw_rst":{"max_time":150.41,"sim_time":2612.066032,"passed":1,"total":1,"percent":100.0},"chip_sw_rstmgr_alert_info":{"max_time":1369.22,"sim_time":14432.954799000001,"passed":1,"total":1,"percent":100.0},"chip_sw_rstmgr_cpu_info":{"max_time":386.98,"sim_time":6382.050429999999,"passed":1,"total":1,"percent":100.0},"chip_sw_pwrmgr_full_aon_reset":{"max_time":67.99,"sim_time":1874.79326,"passed":0,"total":1,"percent":0.0},"chip_sw_pwrmgr_main_power_glitch_reset":{"max_time":239.93,"sim_time":4806.27168,"passed":1,"total":1,"percent":100.0},"chip_sw_pwrmgr_sysrst_ctrl_reset":{"max_time":726.02,"sim_time":7869.065058,"passed":1,"total":1,"percent":100.0},"chip_sw_pwrmgr_all_reset_reqs":{"max_time":892.49,"sim_time":10785.471769,"passed":1,"total":1,"percent":100.0},"chip_sw_pwrmgr_random_sleep_all_reset_reqs":{"max_time":1656.95,"sim_time":21466.165872,"passed":1,"total":1,"percent":100.0},"chip_sw_pwrmgr_deep_sleep_all_reset_reqs":{"max_time":202.12,"sim_time":5735.44,"passed":0,"total":1,"percent":0.0},"chip_sw_pwrmgr_normal_sleep_all_reset_reqs":{"max_time":1015.2,"sim_time":12425.513829,"passed":1,"total":1,"percent":100.0},"chip_sw_pwrmgr_deep_sleep_por_reset":{"max_time":373.68,"sim_time":7158.0708509999995,"passed":1,"total":1,"percent":100.0},"chip_sw_pwrmgr_normal_sleep_por_reset":{"max_time":370.23,"sim_time":5567.274159,"passed":1,"total":1,"percent":100.0},"chip_sw_pwrmgr_sleep_power_glitch_reset":{"max_time":143.72,"sim_time":3101.165133,"passed":0,"total":1,"percent":0.0},"chip_sw_pwrmgr_deep_sleep_power_glitch_reset":{"max_time":425.91,"sim_time":7889.942655,"passed":1,"total":1,"percent":100.0},"chip_sw_pwrmgr_random_sleep_power_glitch_reset":{"max_time":1392.62,"sim_time":19948.343892,"passed":0,"total":1,"percent":0.0},"chip_sw_pwrmgr_sleep_disabled":{"max_time":136.25,"sim_time":3012.3466919999996,"passed":1,"total":1,"percent":100.0},"chip_sw_pwrmgr_usb_clk_disabled_when_active":{"max_time":305.31,"sim_time":4374.211692,"passed":1,"total":1,"percent":100.0},"chip_sw_rv_timer_irq":{"max_time":177.64,"sim_time":3620.904201,"passed":1,"total":1,"percent":100.0},"chip_sw_rv_timer_systick_test":{"max_time":5696.83,"sim_time":38380.160685999996,"passed":1,"total":1,"percent":100.0},"chip_sw_sysrst_ctrl_inputs":{"max_time":125.56,"sim_time":2551.520446,"passed":1,"total":1,"percent":100.0},"chip_sw_sysrst_ctrl_in_irq":{"max_time":355.6,"sim_time":5072.131257,"passed":1,"total":1,"percent":100.0},"chip_sw_sysrst_ctrl_ulp_z3_wakeup":{"max_time":235.12,"sim_time":5445.315232,"passed":1,"total":1,"percent":100.0},"chip_sw_sysrst_ctrl_reset":{"max_time":1260.63,"sim_time":23057.51392,"passed":1,"total":1,"percent":100.0},"chip_sw_sysrst_ctrl_outputs":{"max_time":216.17,"sim_time":4046.5804270000003,"passed":1,"total":1,"percent":100.0},"chip_sw_sysrst_ctrl_ec_rst_l":{"max_time":2378.47,"sim_time":21201.603216,"passed":1,"total":1,"percent":100.0},"chip_sw_aon_timer_irq":{"max_time":235.19,"sim_time":3624.211541,"passed":1,"total":1,"percent":100.0},"chip_sw_aon_timer_sleep_wdog_sleep_pause":{"max_time":238.21,"sim_time":7055.940687,"passed":1,"total":1,"percent":100.0},"chip_sw_aon_timer_wdog_bite_reset":{"max_time":438.6,"sim_time":7699.1825,"passed":0,"total":1,"percent":0.0},"chip_sw_pwrmgr_wdog_reset":{"max_time":369.23,"sim_time":4608.037322,"passed":1,"total":1,"percent":100.0},"chip_sw_aon_timer_wdog_lc_escalate":{"max_time":341.25,"sim_time":5355.882817,"passed":1,"total":1,"percent":100.0},"chip_sw_adc_ctrl_sleep_debug_cable_wakeup":{"max_time":3189.3,"sim_time":34866.379452,"passed":0,"total":1,"percent":0.0},"chip_sw_otbn_randomness":{"max_time":600.66,"sim_time":6350.087028,"passed":1,"total":1,"percent":100.0},"chip_sw_otbn_ecdsa_op_irq":{"max_time":3947.9400000000005,"sim_time":17218.05425,"passed":1,"total":1,"percent":100.0},"chip_sw_otbn_ecdsa_op_irq_jitter_en":{"max_time":3808.45,"sim_time":19050.222829,"passed":1,"total":1,"percent":100.0},"chip_sw_otbn_mem_scramble":{"max_time":277.9,"sim_time":3540.373812,"passed":1,"total":1,"percent":100.0},"chip_sw_rv_core_ibex_rnd":{"max_time":496.80999999999995,"sim_time":4933.2534000000005,"passed":1,"total":1,"percent":100.0},"chip_sw_rv_core_ibex_nmi_irq":{"max_time":491.79,"sim_time":4413.386025000001,"passed":1,"total":1,"percent":100.0},"chip_sw_aes_enc":{"max_time":219.77,"sim_time":3278.3079789999997,"passed":1,"total":1,"percent":100.0},"chip_sw_aes_enc_jitter_en":{"max_time":166.74,"sim_time":3146.288346,"passed":1,"total":1,"percent":100.0},"chip_sw_aes_idle":{"max_time":196.98,"sim_time":3127.360022,"passed":1,"total":1,"percent":100.0},"chip_sw_aes_masking_off":{"max_time":191.01,"sim_time":2589.514361,"passed":1,"total":1,"percent":100.0},"chip_sw_alert_test":{"max_time":202.98,"sim_time":3359.0110449999997,"passed":0,"total":1,"percent":0.0},"chip_sw_alert_handler_escalation":{"max_time":410.36,"sim_time":6036.68196,"passed":1,"total":1,"percent":100.0},"chip_sw_alert_handler_ping_timeout":{"max_time":285.95,"sim_time":4519.746398,"passed":1,"total":1,"percent":100.0},"chip_sw_alert_handler_ping_ok":{"max_time":826.72,"sim_time":7738.0358,"passed":1,"total":1,"percent":100.0},"chip_sw_alert_handler_reverse_ping_in_deep_sleep":{"max_time":8923.5,"sim_time":256242.14386399995,"passed":1,"total":1,"percent":100.0},"chip_sw_alert_handler_lpg_sleep_mode_alerts":{"max_time":154.32,"sim_time":3376.90332,"passed":0,"total":1,"percent":0.0},"chip_sw_alert_handler_lpg_sleep_mode_pings":{"max_time":14400.137158997357,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"chip_sw_alert_handler_lpg_clkoff":{"max_time":1002.9499999999999,"sim_time":8545.11922,"passed":1,"total":1,"percent":100.0},"chip_sw_alert_handler_lpg_reset_toggle":{"max_time":978.9900000000001,"sim_time":8430.751318,"passed":1,"total":1,"percent":100.0},"chip_sw_alert_handler_entropy":{"max_time":189.49,"sim_time":3722.730668,"passed":1,"total":1,"percent":100.0},"chip_sw_aes_entropy":{"max_time":201.83,"sim_time":2893.91714,"passed":1,"total":1,"percent":100.0},"chip_sw_entropy_src_kat_test":{"max_time":154.71,"sim_time":2941.763186,"passed":1,"total":1,"percent":100.0},"chip_sw_edn_auto_mode":{"max_time":483.68,"sim_time":4036.636882,"passed":1,"total":1,"percent":100.0},"chip_sw_edn_boot_mode":{"max_time":336.49,"sim_time":2771.646351,"passed":1,"total":1,"percent":100.0},"chip_sw_edn_kat":{"max_time":239.86,"sim_time":2383.185304,"passed":1,"total":1,"percent":100.0},"chip_sw_edn_sw_mode":{"max_time":989.66,"sim_time":8508.041621999999,"passed":1,"total":1,"percent":100.0},"chip_sw_csrng_lc_hw_debug_en_test":{"max_time":486.88,"sim_time":7840.793633,"passed":1,"total":1,"percent":100.0},"chip_sw_csrng_edn_concurrency":{"max_time":2913.37,"sim_time":16946.84422,"passed":1,"total":1,"percent":100.0},"chip_sw_csrng_kat_test":{"max_time":154.73,"sim_time":2957.5281090000003,"passed":1,"total":1,"percent":100.0},"chip_sw_csrng_fuse_en_sw_app_read_test":{"max_time":235.51,"sim_time":4466.641,"passed":1,"total":1,"percent":100.0},"chip_sw_entropy_src_ast_rng_req":{"max_time":138.02,"sim_time":2953.259287,"passed":1,"total":1,"percent":100.0},"chip_sw_entropy_src_csrng":{"max_time":2129.69,"sim_time":24674.77988,"passed":1,"total":1,"percent":100.0},"chip_sw_edn_entropy_reqs":{"max_time":840.59,"sim_time":7604.799417,"passed":1,"total":1,"percent":100.0},"chip_sw_edn_entropy_reqs_jitter":{"max_time":817.04,"sim_time":7952.218,"passed":1,"total":1,"percent":100.0},"chip_sw_hmac_enc":{"max_time":179.85,"sim_time":2865.655728,"passed":1,"total":1,"percent":100.0},"chip_sw_hmac_enc_jitter_en":{"max_time":163.23,"sim_time":2508.0825299999997,"passed":1,"total":1,"percent":100.0},"chip_sw_hmac_enc_idle":{"max_time":147.76,"sim_time":2744.230142,"passed":1,"total":1,"percent":100.0},"chip_sw_hmac_oneshot":{"max_time":1381.07,"sim_time":9543.88652,"passed":1,"total":1,"percent":100.0},"chip_sw_hmac_multistream":{"max_time":735.21,"sim_time":6273.28675,"passed":1,"total":1,"percent":100.0},"chip_sw_keymgr_key_derivation":{"max_time":1479.12,"sim_time":12261.921505,"passed":1,"total":1,"percent":100.0},"chip_sw_keymgr_key_derivation_prod":{"max_time":1687.61,"sim_time":11814.103872,"passed":1,"total":1,"percent":100.0},"chip_sw_keymgr_key_derivation_jitter_en":{"max_time":1500.9,"sim_time":12420.951002,"passed":1,"total":1,"percent":100.0},"chip_sw_keymgr_sideload_kmac":{"max_time":856.0,"sim_time":7618.052744,"passed":1,"total":1,"percent":100.0},"chip_sw_keymgr_sideload_aes":{"max_time":1181.05,"sim_time":10035.266064,"passed":1,"total":1,"percent":100.0},"chip_sw_keymgr_sideload_otbn":{"max_time":2606.19,"sim_time":13568.11356,"passed":1,"total":1,"percent":100.0},"chip_sw_kmac_mode_cshake":{"max_time":161.37,"sim_time":2251.657479,"passed":1,"total":1,"percent":100.0},"chip_sw_kmac_mode_kmac":{"max_time":184.77,"sim_time":2808.7101719999996,"passed":1,"total":1,"percent":100.0},"chip_sw_kmac_mode_kmac_jitter_en":{"max_time":182.83,"sim_time":3393.7418110000003,"passed":1,"total":1,"percent":100.0},"chip_sw_kmac_app_rom":{"max_time":183.38,"sim_time":3426.406328,"passed":1,"total":1,"percent":100.0},"chip_sw_kmac_idle":{"max_time":128.72,"sim_time":2659.37796,"passed":1,"total":1,"percent":100.0},"chip_sw_rom_ctrl_integrity_check":{"max_time":319.48,"sim_time":9047.647802,"passed":1,"total":1,"percent":100.0},"chip_sw_sram_ctrl_scrambled_access":{"max_time":386.86,"sim_time":4679.705422,"passed":1,"total":1,"percent":100.0},"chip_sw_sram_ctrl_scrambled_access_jitter_en":{"max_time":429.19,"sim_time":5854.084785,"passed":1,"total":1,"percent":100.0},"chip_sw_sram_ctrl_execution_main":{"max_time":581.42,"sim_time":8785.674503,"passed":1,"total":1,"percent":100.0},"chip_sw_sleep_sram_ret_contents_no_scramble":{"max_time":477.21,"sim_time":8937.938672,"passed":1,"total":1,"percent":100.0},"chip_sw_sleep_sram_ret_contents_scramble":{"max_time":590.13,"sim_time":8692.4884,"passed":1,"total":1,"percent":100.0},"chip_sw_sensor_ctrl_alert":{"max_time":527.74,"sim_time":6478.367636,"passed":1,"total":1,"percent":100.0},"chip_sw_sensor_ctrl_status":{"max_time":189.88,"sim_time":3224.46719,"passed":1,"total":1,"percent":100.0},"chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup":{"max_time":245.97,"sim_time":5972.194633,"passed":1,"total":1,"percent":100.0},"chip_sw_coremark":{"max_time":9978.45,"sim_time":71382.325012,"passed":1,"total":1,"percent":100.0},"chip_sw_pwrmgr_b2b_sleep_reset_req":{"max_time":1881.32,"sim_time":20864.194443999997,"passed":1,"total":1,"percent":100.0},"chip_tl_errors":{"max_time":47.19,"sim_time":1954.9112,"passed":0,"total":1,"percent":0.0},"chip_prim_tl_access":{"max_time":190.71,"sim_time":6084.546133999999,"passed":1,"total":1,"percent":100.0},"chip_plic_all_irqs_0":{"max_time":561.35,"sim_time":5677.241076,"passed":1,"total":1,"percent":100.0},"chip_plic_all_irqs_10":{"max_time":260.71,"sim_time":3852.2662530000002,"passed":1,"total":1,"percent":100.0},"chip_plic_all_irqs_20":{"max_time":415.1,"sim_time":4209.348559999999,"passed":1,"total":1,"percent":100.0},"chip_sw_plic_sw_irq":{"max_time":176.11,"sim_time":3176.7567639999997,"passed":1,"total":1,"percent":100.0},"chip_sw_clkmgr_off_peri":{"max_time":648.06,"sim_time":9132.310375,"passed":1,"total":1,"percent":100.0},"chip_sw_clkmgr_off_aes_trans":{"max_time":391.97,"sim_time":5044.07428,"passed":1,"total":1,"percent":100.0},"chip_sw_clkmgr_off_hmac_trans":{"max_time":235.73,"sim_time":4390.749296,"passed":1,"total":1,"percent":100.0},"chip_sw_clkmgr_off_kmac_trans":{"max_time":243.8,"sim_time":3910.35785,"passed":1,"total":1,"percent":100.0},"chip_sw_clkmgr_off_otbn_trans":{"max_time":232.14,"sim_time":4989.006874,"passed":1,"total":1,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_lc":{"max_time":304.09,"sim_time":5853.425719,"passed":1,"total":1,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0":{"max_time":367.86,"sim_time":3804.7507769999997,"passed":1,"total":1,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0":{"max_time":412.48,"sim_time":5255.053831,"passed":1,"total":1,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_fast_dev":{"max_time":377.91,"sim_time":3802.18474,"passed":1,"total":1,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_slow_dev":{"max_time":387.96,"sim_time":4322.305477,"passed":1,"total":1,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_fast_rma":{"max_time":417.76,"sim_time":4144.5898,"passed":1,"total":1,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_slow_rma":{"max_time":417.24,"sim_time":4877.510095,"passed":1,"total":1,"percent":100.0},"chip_sw_clkmgr_reset_frequency":{"max_time":232.92,"sim_time":2815.120462,"passed":1,"total":1,"percent":100.0},"chip_sw_clkmgr_jitter_frequency":{"max_time":270.91,"sim_time":3622.706438,"passed":0,"total":1,"percent":0.0},"chip_sw_clkmgr_jitter":{"max_time":166.46,"sim_time":2819.1769139999997,"passed":1,"total":1,"percent":100.0},"chip_sw_clkmgr_sleep_frequency":{"max_time":413.96,"sim_time":4648.097072,"passed":1,"total":1,"percent":100.0},"chip_jtag_csr_rw":{"max_time":1395.09,"sim_time":17546.004815,"passed":1,"total":1,"percent":100.0},"chip_jtag_mem_access":{"max_time":944.31,"sim_time":14033.373472,"passed":1,"total":1,"percent":100.0},"chip_sw_ast_clk_outputs":{"max_time":650.6,"sim_time":8325.11456,"passed":1,"total":1,"percent":100.0},"chip_sw_lc_ctrl_program_error":{"max_time":386.5,"sim_time":5909.901353,"passed":1,"total":1,"percent":100.0},"chip_sw_pwrmgr_normal_sleep_all_wake_ups":{"max_time":246.12999999999997,"sim_time":7133.020528,"passed":1,"total":1,"percent":100.0},"chip_sw_pwrmgr_lowpower_cancel":{"max_time":256.9,"sim_time":4113.5283500000005,"passed":1,"total":1,"percent":100.0},"chip_sw_pwrmgr_deep_sleep_all_wake_ups":{"max_time":1035.01,"sim_time":25681.876872,"passed":1,"total":1,"percent":100.0},"chip_sw_pwrmgr_random_sleep_all_wake_ups":{"max_time":1018.18,"sim_time":28007.881328000003,"passed":1,"total":1,"percent":100.0},"chip_sw_pwrmgr_sleep_wake_5_bug":{"max_time":10.433266187086701,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up":{"max_time":300.05,"sim_time":6297.549116,"passed":1,"total":1,"percent":100.0},"chip_rv_dm_ndm_reset_req":{"max_time":351.01,"sim_time":5368.819698,"passed":1,"total":1,"percent":100.0},"chip_sw_rv_dm_ndm_reset_req_when_cpu_halted":{"max_time":246.81999999999996,"sim_time":3458.337186,"passed":0,"total":1,"percent":0.0},"chip_sw_rv_dm_access_after_wakeup":{"max_time":295.05,"sim_time":5868.518889000001,"passed":1,"total":1,"percent":100.0},"chip_sw_rv_dm_access_after_escalation_reset":{"max_time":393.39,"sim_time":4770.045669,"passed":1,"total":1,"percent":100.0},"chip_tap_straps_dev":{"max_time":196.06,"sim_time":4169.954531,"passed":1,"total":1,"percent":100.0},"chip_tap_straps_testunlock0":{"max_time":209.73,"sim_time":4199.201411,"passed":1,"total":1,"percent":100.0},"chip_tap_straps_rma":{"max_time":154.89,"sim_time":4099.827303,"passed":1,"total":1,"percent":100.0},"chip_tap_straps_prod":{"max_time":484.6499999999999,"sim_time":9005.484764,"passed":1,"total":1,"percent":100.0},"chip_rv_dm_lc_disabled":{"max_time":46.1,"sim_time":2434.9064909999997,"passed":0,"total":1,"percent":0.0},"chip_sw_rv_core_ibex_address_translation":{"max_time":183.98,"sim_time":3006.023976,"passed":1,"total":1,"percent":100.0},"chip_sw_rv_core_ibex_lockstep_glitch":{"max_time":71.36,"sim_time":2745.346712,"passed":0,"total":1,"percent":0.0},"chip_sw_rv_core_ibex_icache_invalidate":{"max_time":195.09,"sim_time":3460.525798,"passed":1,"total":1,"percent":100.0},"chip_sw_usb_ast_clk_calib":{"max_time":198.59,"sim_time":2921.780121,"passed":1,"total":1,"percent":100.0},"chip_sw_flash_crash_alert":{"max_time":395.35,"sim_time":6347.659467,"passed":1,"total":1,"percent":100.0},"chip_sw_flash_ctrl_write_clear":{"max_time":232.05,"sim_time":3426.0627250000002,"passed":1,"total":1,"percent":100.0},"chip_padctrl_attributes":{"max_time":166.05,"sim_time":4141.811918,"passed":1,"total":1,"percent":100.0},"chip_sw_clkmgr_jitter_reduced_freq":{"max_time":161.7,"sim_time":3279.590371,"passed":1,"total":1,"percent":100.0},"chip_sw_flash_ctrl_ops_jitter_en_reduced_freq":{"max_time":374.26,"sim_time":4797.547421,"passed":1,"total":1,"percent":100.0},"chip_sw_flash_ctrl_access_jitter_en_reduced_freq":{"max_time":620.35,"sim_time":7162.635654,"passed":1,"total":1,"percent":100.0},"chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq":{"max_time":4209.38,"sim_time":25289.697212000003,"passed":1,"total":1,"percent":100.0},"chip_sw_aes_enc_jitter_en_reduced_freq":{"max_time":185.86,"sim_time":3220.02329,"passed":1,"total":1,"percent":100.0},"chip_sw_hmac_enc_jitter_en_reduced_freq":{"max_time":138.23,"sim_time":2843.561532,"passed":1,"total":1,"percent":100.0},"chip_sw_keymgr_key_derivation_jitter_en_reduced_freq":{"max_time":1198.64,"sim_time":11839.740483,"passed":1,"total":1,"percent":100.0},"chip_sw_kmac_mode_kmac_jitter_en_reduced_freq":{"max_time":200.66,"sim_time":3212.168873,"passed":1,"total":1,"percent":100.0},"chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq":{"max_time":368.58,"sim_time":5083.238408,"passed":1,"total":1,"percent":100.0},"chip_sw_flash_init_reduced_freq":{"max_time":1240.87,"sim_time":23332.134145,"passed":1,"total":1,"percent":100.0},"chip_sw_csrng_edn_concurrency_reduced_freq":{"max_time":4488.1,"sim_time":31688.176976,"passed":1,"total":1,"percent":100.0},"chip_sw_power_idle_load":{"max_time":231.51,"sim_time":3837.402,"passed":0,"total":1,"percent":0.0},"chip_sw_power_sleep_load":{"max_time":191.51,"sim_time":3493.779,"passed":0,"total":1,"percent":0.0},"chip_sw_ast_clk_rst_inputs":{"max_time":1016.97,"sim_time":11120.113893,"passed":0,"total":1,"percent":0.0},"chip_sw_power_virus":{"max_time":1099.96,"sim_time":6641.738874,"passed":1,"total":1,"percent":100.0},"chip_sw_flash_scrambling_smoketest":{"max_time":167.19,"sim_time":2629.556508,"passed":1,"total":1,"percent":100.0},"chip_sw_flash_ctrl_mem_protection":{"max_time":575.24,"sim_time":5374.4049939999995,"passed":1,"total":1,"percent":100.0},"ate_bootstrap_flash_erase":{"max_time":606.95,"sim_time":10010.260001,"passed":0,"total":1,"percent":0.0},"ate_bootstrap_one_frame":{"max_time":6673.09,"sim_time":45611.797413,"passed":1,"total":1,"percent":100.0},"ate_bootstrap_disjoint":{"max_time":9882.57,"sim_time":85162.240507,"passed":1,"total":1,"percent":100.0},"rom_e2e_smoke":{"max_time":3115.05,"sim_time":15243.726288,"passed":1,"total":1,"percent":100.0},"rom_e2e_shutdown_exception_c":{"max_time":2912.89,"sim_time":15365.382754,"passed":1,"total":1,"percent":100.0},"rom_e2e_shutdown_output":{"max_time":2648.87,"sim_time":25628.917404,"passed":1,"total":1,"percent":100.0},"rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0":{"max_time":56.32704469934106,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_good_b_good_dev":{"max_time":27.6703048851341,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_good_b_good_prod":{"max_time":20.889628702774644,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_good_b_good_prod_end":{"max_time":29.84745849482715,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_good_b_good_rma":{"max_time":22.177847100421786,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0":{"max_time":121.92506842501462,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_good_b_bad_dev":{"max_time":45.88465062528849,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_good_b_bad_prod":{"max_time":24.83833589218557,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_good_b_bad_prod_end":{"max_time":40.742302522063255,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_good_b_bad_rma":{"max_time":12.24280577711761,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0":{"max_time":210.22519324347377,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_bad_b_good_dev":{"max_time":85.83223608508706,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_bad_b_good_prod":{"max_time":70.04168225079775,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_bad_b_good_prod_end":{"max_time":152.72001906856894,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_bad_b_good_rma":{"max_time":68.18357366509736,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0":{"max_time":19.47,"sim_time":10.360001,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_bad_b_bad_dev":{"max_time":18.54,"sim_time":10.220001,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_bad_b_bad_prod":{"max_time":19.87,"sim_time":10.100001,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_bad_b_bad_prod_end":{"max_time":20.16,"sim_time":10.140001,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_bad_b_bad_rma":{"max_time":19.45,"sim_time":10.340001,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0":{"max_time":21.37,"sim_time":10.180001,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_bad_b_nothing_dev":{"max_time":22.26,"sim_time":10.360001,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_bad_b_nothing_prod":{"max_time":25.7,"sim_time":10.220001,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_bad_b_nothing_prod_end":{"max_time":20.25,"sim_time":10.280001,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_bad_b_nothing_rma":{"max_time":19.52,"sim_time":10.120001,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0":{"max_time":19.23,"sim_time":10.400001,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_nothing_b_bad_dev":{"max_time":21.46,"sim_time":10.360001,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_nothing_b_bad_prod":{"max_time":25.68,"sim_time":10.160001,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_nothing_b_bad_prod_end":{"max_time":19.22,"sim_time":10.380001,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_nothing_b_bad_rma":{"max_time":18.98,"sim_time":10.320001,"passed":0,"total":1,"percent":0.0},"rom_e2e_asm_init_test_unlocked0":{"max_time":65.66882321983576,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_asm_init_dev":{"max_time":24.334684198722243,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_asm_init_prod":{"max_time":70.99129133298993,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_asm_init_prod_end":{"max_time":66.92736869677901,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_asm_init_rma":{"max_time":75.07562765292823,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_jtag_debug_test_unlocked0":{"max_time":188.65,"sim_time":4343.506508,"passed":0,"total":1,"percent":0.0},"rom_e2e_jtag_debug_dev":{"max_time":507.88,"sim_time":7463.137275,"passed":0,"total":1,"percent":0.0},"rom_e2e_jtag_debug_rma":{"max_time":437.12,"sim_time":7632.110446000001,"passed":0,"total":1,"percent":0.0},"rom_e2e_jtag_inject_test_unlocked0":{"max_time":65.14,"sim_time":2646.998731,"passed":0,"total":1,"percent":0.0},"rom_e2e_jtag_inject_dev":{"max_time":75.1,"sim_time":2563.6369360000003,"passed":0,"total":1,"percent":0.0},"rom_e2e_jtag_inject_rma":{"max_time":89.59,"sim_time":2610.409009,"passed":0,"total":1,"percent":0.0},"rom_e2e_static_critical":{"max_time":3208.38,"sim_time":16327.777995999999,"passed":1,"total":1,"percent":100.0},"rom_e2e_keymgr_init_rom_ext_meas":{"max_time":3162.33,"sim_time":20909.769429,"passed":0,"total":1,"percent":0.0},"rom_e2e_keymgr_init_rom_ext_no_meas":{"max_time":5970.49,"sim_time":30076.013969,"passed":1,"total":1,"percent":100.0},"rom_e2e_keymgr_init_rom_ext_invalid_meas":{"max_time":5921.32,"sim_time":28477.603817000003,"passed":1,"total":1,"percent":100.0},"rom_volatile_raw_unlock":{"max_time":40.62764375656843,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_raw_unlock":{"max_time":187.84743232652545,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_self_hash":{"max_time":53.37517907097936,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_keymgr_functest":{"max_time":357.08,"sim_time":4522.62097,"passed":0,"total":1,"percent":0.0},"chip_sw_aes_smoketest":{"max_time":211.57,"sim_time":3735.0290099999997,"passed":1,"total":1,"percent":100.0},"chip_sw_aon_timer_smoketest":{"max_time":205.03,"sim_time":3560.236671,"passed":1,"total":1,"percent":100.0},"chip_sw_clkmgr_smoketest":{"max_time":166.77,"sim_time":3440.66664,"passed":1,"total":1,"percent":100.0},"chip_sw_csrng_smoketest":{"max_time":179.43,"sim_time":3081.12887,"passed":1,"total":1,"percent":100.0},"chip_sw_entropy_src_smoketest":{"max_time":835.5,"sim_time":7265.301005,"passed":1,"total":1,"percent":100.0},"chip_sw_gpio_smoketest":{"max_time":234.11,"sim_time":2942.752236,"passed":1,"total":1,"percent":100.0},"chip_sw_hmac_smoketest":{"max_time":240.83,"sim_time":3672.83563,"passed":1,"total":1,"percent":100.0},"chip_sw_kmac_smoketest":{"max_time":220.52,"sim_time":3174.0766869999998,"passed":1,"total":1,"percent":100.0},"chip_sw_otbn_smoketest":{"max_time":972.6700000000001,"sim_time":8090.094088000001,"passed":1,"total":1,"percent":100.0},"chip_sw_otp_ctrl_smoketest":{"max_time":194.69,"sim_time":3099.6285070000004,"passed":1,"total":1,"percent":100.0},"chip_sw_pwrmgr_smoketest":{"max_time":198.59,"sim_time":5211.95748,"passed":1,"total":1,"percent":100.0},"chip_sw_pwrmgr_usbdev_smoketest":{"max_time":314.07,"sim_time":5897.056616000001,"passed":1,"total":1,"percent":100.0},"chip_sw_rv_plic_smoketest":{"max_time":134.73,"sim_time":2315.90978,"passed":1,"total":1,"percent":100.0},"chip_sw_rv_timer_smoketest":{"max_time":190.25,"sim_time":4022.0734660000003,"passed":1,"total":1,"percent":100.0},"chip_sw_rstmgr_smoketest":{"max_time":210.76,"sim_time":2929.6119900000003,"passed":1,"total":1,"percent":100.0},"chip_sw_sram_ctrl_smoketest":{"max_time":182.55,"sim_time":3020.677659,"passed":1,"total":1,"percent":100.0},"chip_sw_uart_smoketest":{"max_time":212.2,"sim_time":3193.827972,"passed":1,"total":1,"percent":100.0},"xbar_smoke":{"max_time":4.69,"sim_time":48.520502,"passed":1,"total":1,"percent":100.0},"xbar_smoke_zero_delays":{"max_time":5.88,"sim_time":47.195724999999996,"passed":1,"total":1,"percent":100.0},"xbar_smoke_large_delays":{"max_time":39.46,"sim_time":6228.100479000001,"passed":1,"total":1,"percent":100.0},"xbar_smoke_slow_rsp":{"max_time":41.89,"sim_time":4398.377519000001,"passed":1,"total":1,"percent":100.0},"xbar_random":{"max_time":48.51,"sim_time":2089.0642620000003,"passed":1,"total":1,"percent":100.0},"xbar_random_zero_delays":{"max_time":15.32,"sim_time":213.73201999999998,"passed":1,"total":1,"percent":100.0},"xbar_random_large_delays":{"max_time":94.69,"sim_time":15880.511925,"passed":1,"total":1,"percent":100.0},"xbar_random_slow_rsp":{"max_time":149.69,"sim_time":16851.265868000002,"passed":1,"total":1,"percent":100.0},"xbar_access_same_device":{"max_time":36.66,"sim_time":1187.365368,"passed":1,"total":1,"percent":100.0},"xbar_access_same_device_slow_rsp":{"max_time":117.15,"sim_time":12466.910154,"passed":1,"total":1,"percent":100.0},"xbar_same_source":{"max_time":20.18,"sim_time":349.408885,"passed":1,"total":1,"percent":100.0},"xbar_error_random":{"max_time":14.41,"sim_time":234.756921,"passed":1,"total":1,"percent":100.0},"xbar_unmapped_addr":{"max_time":4.1,"sim_time":39.11283,"passed":1,"total":1,"percent":100.0},"xbar_error_and_unmapped_addr":{"max_time":29.78,"sim_time":1133.845051,"passed":1,"total":1,"percent":100.0},"xbar_stress_all":{"max_time":187.5,"sim_time":3230.813914,"passed":1,"total":1,"percent":100.0},"xbar_stress_all_with_rand_reset":{"max_time":603.84,"sim_time":8864.936637,"passed":1,"total":1,"percent":100.0},"xbar_stress_all_with_error":{"max_time":163.27,"sim_time":3410.267491,"passed":1,"total":1,"percent":100.0},"xbar_stress_all_with_reset_error":{"max_time":228.27,"sim_time":5956.776138,"passed":1,"total":1,"percent":100.0},"chip_csr_hw_reset":{"max_time":259.6,"sim_time":7009.401744,"passed":1,"total":1,"percent":100.0},"chip_csr_rw":{"max_time":247.25,"sim_time":4691.388056,"passed":1,"total":1,"percent":100.0},"chip_csr_mem_rw_with_rand_reset":{"max_time":356.49,"sim_time":6176.211053999999,"passed":1,"total":1,"percent":100.0}},"passed":253,"total":329,"percent":76.89969604863222}},"passed":253,"total":329,"percent":76.89969604863222}},"coverage":{"code":{"block":null,"line_statement":94.42,"branch":93.85,"condition_expression":89.74,"toggle":91.29,"fsm":57.14},"assertion":97.25,"functional":50.33},"cov_report_page":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/cov_report/dashboard.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected *, got *":[{"name":"chip_sw_all_escalation_resets","qual_name":"0.chip_sw_all_escalation_resets.109424374510589518829577209559502755918322218375492735665038833009090087267048","seed":109424374510589518829577209559502755918322218375492735665038833009090087267048,"line":317,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 3216.018180 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *rstmgr_aon.u_d0_spi_host*.leaf_rst_path":[{"name":"chip_sw_rstmgr_rst_cnsty_escalation","qual_name":"0.chip_sw_rstmgr_rst_cnsty_escalation.64237407536702210398465701204628138448992164633989200602011249247794383865779","seed":64237407536702210398465701204628138448992164633989200602011249247794383865779,"line":301,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_rst_cnsty_escalation/latest/run.log","log_context":["UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty":[{"name":"chip_sw_spi_device_pass_through_collision","qual_name":"0.chip_sw_spi_device_pass_through_collision.50963939749888462305244836186843219170050341927103553204736560556494246036610","seed":50963939749888462305244836186843219170050341927103553204736560556494246036610,"line":327,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log","log_context":["UVM_INFO @ 3566.542140 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected":[{"name":"chip_sw_flash_ctrl_lc_rw_en","qual_name":"0.chip_sw_flash_ctrl_lc_rw_en.89676135138368337372196285581706085886779013525575408557609654419571149781495","seed":89676135138368337372196285581706085886779013525575408557609654419571149781495,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_lc_rw_en/latest/run.log","log_context":["UVM_INFO @ 3279.309427 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *":[{"name":"chip_sw_otp_ctrl_lc_signals_rma","qual_name":"0.chip_sw_otp_ctrl_lc_signals_rma.60537505123818452561468446729728806854940350650757608642385851697048977605520","seed":60537505123818452561468446729728806854940350650757608642385851697048977605520,"line":342,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log","log_context":["UVM_INFO @ 5278.721192 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'":[{"name":"chip_sw_otp_ctrl_escalation","qual_name":"0.chip_sw_otp_ctrl_escalation.20703259326302423844822564444284402578896241748245464829849995660871166741147","seed":20703259326302423844822564444284402578896241748245464829849995660871166741147,"line":316,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log","log_context":["UVM_ERROR @ 3368.201632 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A\n","UVM_INFO @ 3368.201632 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode":[{"name":"chip_sw_otp_ctrl_rot_auth_config","qual_name":"0.chip_sw_otp_ctrl_rot_auth_config.74252057241154758582815915786682299624216052371123824306606135140618962418638","seed":74252057241154758582815915786682299624216052371123824306606135140618962418638,"line":282,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_rot_auth_config/latest/run.log","log_context":["UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (chip_sw_base_vseq.sv:864) virtual_sequencer [chip_sw_lc_walkthrough_vseq] max attempt reached to get lc status LcExtClockSwitched!":[{"name":"chip_sw_lc_walkthrough_dev","qual_name":"0.chip_sw_lc_walkthrough_dev.20207011500582837832166266540402728417389635918779872037422212739872516870083","seed":20207011500582837832166266540402728417389635918779872037422212739872516870083,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_dev/latest/run.log","log_context":["UVM_INFO @ 26374.713656 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected":[{"name":"chip_sw_lc_walkthrough_prod","qual_name":"0.chip_sw_lc_walkthrough_prod.37287100516370862009981787830318872447061148112593048034263666983919799235710","seed":37287100516370862009981787830318872447061148112593048034263666983919799235710,"line":369,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_prod/latest/run.log","log_context":["UVM_INFO @ 7616.632570 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_rma","qual_name":"0.chip_sw_lc_walkthrough_rma.57481954600511146632074560931336685666321518717647860103471676494823344880761","seed":57481954600511146632074560931336685666321518717647860103471676494823344880761,"line":341,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_rma/latest/run.log","log_context":["UVM_INFO @ 7246.608434 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (chip_sw_base_vseq.sv:864) virtual_sequencer [chip_sw_lc_volatile_raw_unlock_vseq] max attempt reached to get lc status LcTokenError!":[{"name":"chip_sw_lc_ctrl_volatile_raw_unlock","qual_name":"0.chip_sw_lc_ctrl_volatile_raw_unlock.22682175253513493032192759385516662196509112932700097618439164148395224230048","seed":22682175253513493032192759385516662196509112932700097618439164148395224230048,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_volatile_raw_unlock/latest/run.log","log_context":["UVM_INFO @ 26888.532084 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Offending '((~rst_ni) === (~seed_en_q))'":[{"name":"chip_sw_pwrmgr_full_aon_reset","qual_name":"0.chip_sw_pwrmgr_full_aon_reset.83694365722974517173069269374102135286940000098984689265911667323113733250175","seed":83694365722974517173069269374102135286940000098984689265911667323113733250175,"line":303,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_full_aon_reset/latest/run.log","log_context":["UVM_ERROR @ 1874.793260 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A\n","UVM_INFO @ 1874.793260 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"Offending '(rstreqs[*] && (reset_cause == HwReq))'":[{"name":"chip_sw_pwrmgr_deep_sleep_all_reset_reqs","qual_name":"0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.27157203521567092260058432937018934498522998635287653452790956829695835290878","seed":27157203521567092260058432937018934498522998635287653452790956829695835290878,"line":314,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest/run.log","log_context":["UVM_ERROR @ 5735.440000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 5735.440000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_aon_timer_wdog_bite_reset","qual_name":"0.chip_sw_aon_timer_wdog_bite_reset.86275574691672831173240997528590080523706933445872089299819244707282885117753","seed":86275574691672831173240997528590080523706933445872089299819244707282885117753,"line":319,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log","log_context":["UVM_ERROR @ 7699.182500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 7699.182500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))'":[{"name":"chip_sw_pwrmgr_sleep_power_glitch_reset","qual_name":"0.chip_sw_pwrmgr_sleep_power_glitch_reset.21775687359542574377736769939945638377573583329646160194356600507674088748871","seed":21775687359542574377736769939945638377573583329646160194356600507674088748871,"line":313,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_power_glitch_reset/latest/run.log","log_context":["UVM_ERROR @ 3101.165133 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A\n","UVM_INFO @ 3101.165133 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_random_sleep_power_glitch_reset","qual_name":"0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.47346295694707473351919593912846003259932668013921616769997349278978850707362","seed":47346295694707473351919593912846003259932668013921616769997349278978850707362,"line":395,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/run.log","log_context":["UVM_ERROR @ 19948.343892 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A\n","UVM_INFO @ 19948.343892 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns":[{"name":"chip_sw_adc_ctrl_sleep_debug_cable_wakeup","qual_name":"0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.27494845778315085071620025371862354141746840975812477537635978752101663200353","seed":27494845778315085071620025371862354141746840975812477537635978752101663200353,"line":332,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log","log_context":["\n","UVM_INFO @ 34866.379452 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *!":[{"name":"chip_sw_alert_test","qual_name":"0.chip_sw_alert_test.73108579535849932805705004931140310259192900301249591962082986097153505761370","seed":73108579535849932805705004931140310259192900301249591962082986097153505761370,"line":307,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log","log_context":["UVM_INFO @ 3359.011045 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)":[{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"0.chip_sw_alert_handler_lpg_sleep_mode_alerts.24703225684319895952289915301943415262722683034525883927364839699610453812453","seed":24703225684319895952289915301943415262722683034525883927364839699610453812453,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3376.903320 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Job timed out after * minutes":[{"name":"chip_sw_alert_handler_lpg_sleep_mode_pings","qual_name":"0.chip_sw_alert_handler_lpg_sleep_mode_pings.82257661305835647565372657020907624522306247699454166884342789580967125773642","seed":82257661305835647565372657020907624522306247699454166884342789580967125773642,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log","log_context":[]}],"UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *).":[{"name":"chip_tl_errors","qual_name":"0.chip_tl_errors.12199061693023276707695792015855555416017786105648253791961897436821720704270","seed":12199061693023276707695792015855555416017786105648253791961897436821720704270,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@31688) { a_addr: 'h106dc  a_data: 'hee42b25f  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h4  a_user: 'h1ba19  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 1954.911200 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected":[{"name":"chip_sw_clkmgr_jitter_frequency","qual_name":"0.chip_sw_clkmgr_jitter_frequency.12863669956846531135668847260006031628299337402306967049738346456295484563342","seed":12863669956846531135668847260006031628299337402306967049738346456295484563342,"line":343,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_jitter_frequency/latest/run.log","log_context":["UVM_INFO @ 3622.706438 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']":[{"name":"chip_sw_pwrmgr_sleep_wake_5_bug","qual_name":"0.chip_sw_pwrmgr_sleep_wake_5_bug.31361552707308513943666013200029644290981902418814272725672284269909202845363","seed":31361552707308513943666013200029644290981902418814272725672284269909202845363,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=2071322) is running. Waiting for it to complete on the server (server_pid=269160)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.63267312920783635020005937921371284678593657658417118862152656323826736331854","seed":63267312920783635020005937921371284678593657658417118862152656323826736331854,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest/run.log","log_context":["Another command (pid=411190) is running. Waiting for it to complete on the server (server_pid=269160)...\n","Another command (pid=419105) is running. Waiting for it to complete on the server (server_pid=269160)...\n","Another command (pid=370080) is running. Waiting for it to complete on the server (server_pid=269160)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_good_dev","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_good_dev.78389972501038462934403975615691607637210038679114082377264058130186745620322","seed":78389972501038462934403975615691607637210038679114082377264058130186745620322,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest/run.log","log_context":["Another command (pid=588079) is running. Waiting for it to complete on the server (server_pid=269160)...\n","Another command (pid=576623) is running. Waiting for it to complete on the server (server_pid=269160)...\n","Another command (pid=588818) is running. Waiting for it to complete on the server (server_pid=269160)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_good_prod","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_good_prod.13428004467571277130766598915277008574454233013591145216241962763492990918766","seed":13428004467571277130766598915277008574454233013591145216241962763492990918766,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_prod/latest/run.log","log_context":["Another command (pid=396879) is running. Waiting for it to complete on the server (server_pid=269160)...\n","Another command (pid=554894) is running. Waiting for it to complete on the server (server_pid=269160)...\n","Another command (pid=563990) is running. Waiting for it to complete on the server (server_pid=269160)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_good_prod_end","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.30930193501128528724144308875489347565563992514232050390856194590059585496956","seed":30930193501128528724144308875489347565563992514232050390856194590059585496956,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end/latest/run.log","log_context":["Another command (pid=597912) is running. Waiting for it to complete on the server (server_pid=269160)...\n","Another command (pid=470710) is running. Waiting for it to complete on the server (server_pid=269160)...\n","Another command (pid=602591) is running. Waiting for it to complete on the server (server_pid=269160)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_good_rma","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_good_rma.107300449915092456022824490536181714709307803370802636052951232044577679545957","seed":107300449915092456022824490536181714709307803370802636052951232044577679545957,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_rma/latest/run.log","log_context":["Another command (pid=582264) is running. Waiting for it to complete on the server (server_pid=269160)...\n","Another command (pid=576623) is running. Waiting for it to complete on the server (server_pid=269160)...\n","Another command (pid=588818) is running. Waiting for it to complete on the server (server_pid=269160)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.98665564256597446563679036378239399373493771624981741430752162994684266231965","seed":98665564256597446563679036378239399373493771624981741430752162994684266231965,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log","log_context":["Another command (pid=451139) is running. Waiting for it to complete on the server (server_pid=269160)...\n","Another command (pid=453437) is running. Waiting for it to complete on the server (server_pid=269160)...\n","Another command (pid=378496) is running. Waiting for it to complete on the server (server_pid=269160)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_bad_dev","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.37975039637558691800574648766269556677890043650037682279016910700732638534845","seed":37975039637558691800574648766269556677890043650037682279016910700732638534845,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log","log_context":["Another command (pid=451139) is running. Waiting for it to complete on the server (server_pid=269160)...\n","Another command (pid=453437) is running. Waiting for it to complete on the server (server_pid=269160)...\n","Another command (pid=378496) is running. Waiting for it to complete on the server (server_pid=269160)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_bad_prod","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.33532300649986411871748687445224652396346026543705624410185716143931758128692","seed":33532300649986411871748687445224652396346026543705624410185716143931758128692,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log","log_context":["Another command (pid=453437) is running. Waiting for it to complete on the server (server_pid=269160)...\n","Another command (pid=421806) is running. Waiting for it to complete on the server (server_pid=269160)...\n","Another command (pid=543432) is running. Waiting for it to complete on the server (server_pid=269160)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_bad_prod_end","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.87928742764077558978896813636425953546425818125578649265782109179921289078274","seed":87928742764077558978896813636425953546425818125578649265782109179921289078274,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log","log_context":["Another command (pid=396879) is running. Waiting for it to complete on the server (server_pid=269160)...\n","Another command (pid=554894) is running. Waiting for it to complete on the server (server_pid=269160)...\n","Another command (pid=563990) is running. Waiting for it to complete on the server (server_pid=269160)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_bad_rma","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.107799502692316053433211194113242256432784416685697373117701810611767515875552","seed":107799502692316053433211194113242256432784416685697373117701810611767515875552,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log","log_context":["Another command (pid=560628) is running. Waiting for it to complete on the server (server_pid=269160)...\n","Another command (pid=545254) is running. Waiting for it to complete on the server (server_pid=269160)...\n","Another command (pid=562198) is running. Waiting for it to complete on the server (server_pid=269160)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0","qual_name":"0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.113663571192098564820689935317197554429399654110475610673588761806405326711680","seed":113663571192098564820689935317197554429399654110475610673588761806405326711680,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log","log_context":["Another command (pid=709298) is running. Waiting for it to complete on the server (server_pid=269160)...\n","Another command (pid=716090) is running. Waiting for it to complete on the server (server_pid=269160)...\n","Another command (pid=720393) is running. Waiting for it to complete on the server (server_pid=269160)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_bad_b_good_dev","qual_name":"0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.22978381074059233208835956477308137272904177159205273375501473845419430804802","seed":22978381074059233208835956477308137272904177159205273375501473845419430804802,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log","log_context":["Another command (pid=563990) is running. Waiting for it to complete on the server (server_pid=269160)...\n","Another command (pid=527143) is running. Waiting for it to complete on the server (server_pid=269160)...\n","Another command (pid=572160) is running. Waiting for it to complete on the server (server_pid=269160)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_bad_b_good_prod","qual_name":"0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.94635416857541385582558011421891931149612657133608881488696700978642107426710","seed":94635416857541385582558011421891931149612657133608881488696700978642107426710,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=551669) is running. Waiting for it to complete on the server (server_pid=269160)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_bad_b_good_prod_end","qual_name":"0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.10532504429438281580704082247588866478963382955212666137057892959150791537107","seed":10532504429438281580704082247588866478963382955212666137057892959150791537107,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log","log_context":["Another command (pid=692065) is running. Waiting for it to complete on the server (server_pid=269160)...\n","Another command (pid=735276) is running. Waiting for it to complete on the server (server_pid=269160)...\n","Another command (pid=600217) is running. Waiting for it to complete on the server (server_pid=269160)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_bad_b_good_rma","qual_name":"0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.101663646500824163186286927936519335554741407537673765884381186239330444999610","seed":101663646500824163186286927936519335554741407537673765884381186239330444999610,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log","log_context":["Another command (pid=562198) is running. Waiting for it to complete on the server (server_pid=269160)...\n","Another command (pid=560727) is running. Waiting for it to complete on the server (server_pid=269160)...\n","Another command (pid=554894) is running. Waiting for it to complete on the server (server_pid=269160)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_test_unlocked0","qual_name":"0.rom_e2e_asm_init_test_unlocked0.94494578632895787557200601262979483163883035743493253993078366611773667093037","seed":94494578632895787557200601262979483163883035743493253993078366611773667093037,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_test_unlocked0/latest/run.log","log_context":["Another command (pid=419105) is running. Waiting for it to complete on the server (server_pid=269160)...\n","Another command (pid=370080) is running. Waiting for it to complete on the server (server_pid=269160)...\n","Another command (pid=387477) is running. Waiting for it to complete on the server (server_pid=269160)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_dev","qual_name":"0.rom_e2e_asm_init_dev.12176988856156559233747280707560826157657729856678255104273038551174288883235","seed":12176988856156559233747280707560826157657729856678255104273038551174288883235,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_dev/latest/run.log","log_context":["Another command (pid=403410) is running. Waiting for it to complete on the server (server_pid=269160)...\n","Another command (pid=411190) is running. Waiting for it to complete on the server (server_pid=269160)...\n","Another command (pid=419105) is running. Waiting for it to complete on the server (server_pid=269160)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_prod","qual_name":"0.rom_e2e_asm_init_prod.101454636564418133843003590351126256610287560952620759099120213508020285367640","seed":101454636564418133843003590351126256610287560952620759099120213508020285367640,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_prod/latest/run.log","log_context":["Another command (pid=408498) is running. Waiting for it to complete on the server (server_pid=269160)...\n","Another command (pid=453879) is running. Waiting for it to complete on the server (server_pid=269160)...\n","Another command (pid=455052) is running. Waiting for it to complete on the server (server_pid=269160)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_prod_end","qual_name":"0.rom_e2e_asm_init_prod_end.64196232389533693556482082936421737207777928573480046372989537127112468357497","seed":64196232389533693556482082936421737207777928573480046372989537127112468357497,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_prod_end/latest/run.log","log_context":["Another command (pid=489210) is running. Waiting for it to complete on the server (server_pid=269160)...\n","Another command (pid=480845) is running. Waiting for it to complete on the server (server_pid=269160)...\n","Another command (pid=469790) is running. Waiting for it to complete on the server (server_pid=269160)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_rma","qual_name":"0.rom_e2e_asm_init_rma.46920358671894794055682195561958730072897434002962932826361504566661645421888","seed":46920358671894794055682195561958730072897434002962932826361504566661645421888,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_rma/latest/run.log","log_context":["Another command (pid=558711) is running. Waiting for it to complete on the server (server_pid=269160)...\n","Another command (pid=560628) is running. Waiting for it to complete on the server (server_pid=269160)...\n","Another command (pid=545254) is running. Waiting for it to complete on the server (server_pid=269160)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_volatile_raw_unlock","qual_name":"0.rom_volatile_raw_unlock.22252249169567619795523546441497705888965134580295041063303544349712287384711","seed":22252249169567619795523546441497705888965134580295041063303544349712287384711,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_volatile_raw_unlock/latest/run.log","log_context":["---- STDERR ----\n","Another command (pid=363896) is running. Waiting for it to complete on the server (server_pid=269160)...\n","Another command (pid=396633) is running. Waiting for it to complete on the server (server_pid=269160)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_raw_unlock","qual_name":"0.rom_raw_unlock.96398610906619741000888358096497017859066878640917123785586996318122987144336","seed":96398610906619741000888358096497017859066878640917123785586996318122987144336,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_raw_unlock/latest/run.log","log_context":["Another command (pid=686990) is running. Waiting for it to complete on the server (server_pid=269160)...\n","Another command (pid=599969) is running. Waiting for it to complete on the server (server_pid=269160)...\n","Another command (pid=676812) is running. Waiting for it to complete on the server (server_pid=269160)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_self_hash","qual_name":"0.rom_e2e_self_hash.100174016927720682492477741095650020176317353286629724482741929250638116809166","seed":100174016927720682492477741095650020176317353286629724482741929250638116809166,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log","log_context":["Another command (pid=419105) is running. Waiting for it to complete on the server (server_pid=269160)...\n","Another command (pid=370080) is running. Waiting for it to complete on the server (server_pid=269160)...\n","Another command (pid=387477) is running. Waiting for it to complete on the server (server_pid=269160)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]}],"Error-[NOA] Null object access":[{"name":"chip_sw_rv_dm_ndm_reset_req_when_cpu_halted","qual_name":"0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.100606263535381963180844568791442387242224546071559594808839095360096460060235","seed":100606263535381963180844568791442387242224546071559594808839095360096460060235,"line":327,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"rom_e2e_jtag_debug_test_unlocked0","qual_name":"0.rom_e2e_jtag_debug_test_unlocked0.104804869092075785379159618533322260281792188421430895446946780559484246655588","seed":104804869092075785379159618533322260281792188421430895446946780559484246655588,"line":319,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"rom_e2e_jtag_debug_dev","qual_name":"0.rom_e2e_jtag_debug_dev.2791610199532073317097036320226296500564240595473360218469026657697066543549","seed":2791610199532073317097036320226296500564240595473360218469026657697066543549,"line":352,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"rom_e2e_jtag_debug_rma","qual_name":"0.rom_e2e_jtag_debug_rma.2795119774793051092647365107762317350613977482457870333779367757137625211789","seed":2795119774793051092647365107762317350613977482457870333779367757137625211789,"line":352,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"rom_e2e_jtag_inject_test_unlocked0","qual_name":"0.rom_e2e_jtag_inject_test_unlocked0.106995529071994353744947343829359446234263336246317100380173301578328816578943","seed":106995529071994353744947343829359446234263336246317100380173301578328816578943,"line":303,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_test_unlocked0/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"rom_e2e_jtag_inject_dev","qual_name":"0.rom_e2e_jtag_inject_dev.68203885061414023114503479383084558839576977075561333450850556734233062523574","seed":68203885061414023114503479383084558839576977075561333450850556734233062523574,"line":305,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_dev/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"rom_e2e_jtag_inject_rma","qual_name":"0.rom_e2e_jtag_inject_rma.113442169214178981905643220816059151902816625062288139388666465800364786065915","seed":113442169214178981905643220816059151902816625062288139388666465800364786065915,"line":307,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_rma/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]}],"UVM_ERROR @ * us: (cip_base_vseq.sv:660) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch":[{"name":"chip_rv_dm_lc_disabled","qual_name":"0.chip_rv_dm_lc_disabled.46914459322301968588618188568513708454711678849633289391909753456435553639104","seed":46914459322301968588618188568513708454711678849633289391909753456435553639104,"line":216,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log","log_context":["UVM_INFO @ 2434.906491 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:738) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation.":[{"name":"chip_sw_rv_core_ibex_lockstep_glitch","qual_name":"0.chip_sw_rv_core_ibex_lockstep_glitch.10613884699787521889955752776764504700181285595882705461167191238312588867622","seed":10613884699787521889955752776764504700181285595882705461167191238312588867622,"line":324,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log","log_context":["UVM_INFO @ 2745.346712 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *":[{"name":"chip_sw_power_idle_load","qual_name":"0.chip_sw_power_idle_load.76477781273750717546916002805067359637990029016565576645131138080309098243968","seed":76477781273750717546916002805067359637990029016565576645131138080309098243968,"line":312,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log","log_context":["UVM_INFO @ 3837.402000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *":[{"name":"chip_sw_power_sleep_load","qual_name":"0.chip_sw_power_sleep_load.27875008484474790876069210366398039781079285603652744296926280305104737866068","seed":27875008484474790876069210366398039781079285603652744296926280305104737866068,"line":318,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log","log_context":["UVM_INFO @ 3493.779000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *":[{"name":"chip_sw_ast_clk_rst_inputs","qual_name":"0.chip_sw_ast_clk_rst_inputs.34179045039148588618416637004739568294995838909281426662861292821054283794644","seed":34179045039148588618416637004739568294995838909281426662861292821054283794644,"line":327,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log","log_context":["UVM_INFO @ 11120.113893 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_*.opcode (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1)":[{"name":"ate_bootstrap_flash_erase","qual_name":"0.ate_bootstrap_flash_erase.74819299969885262287714791859513886744435783610579031993779722308923596421157","seed":74819299969885262287714791859513886744435783610579031993779722308923596421157,"line":272,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.ate_bootstrap_flash_erase/latest/run.log","log_context":["UVM_INFO @ 10010.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode":[{"name":"rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.65103547106724976657816053999153499093507080571242557761410820404712935651012","seed":65103547106724976657816053999153499093507080571242557761410820404712935651012,"line":363,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log","log_context":["UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.91864945468378621484023455021684966031498505271062254307929521535573815822640","seed":91864945468378621484023455021684966031498505271062254307929521535573815822640,"line":326,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log","log_context":["UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode":[{"name":"rom_e2e_sigverify_always_a_bad_b_bad_dev","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_bad_dev.15232315866134967215252515168620387372061245411590394501381262361357660591775","seed":15232315866134967215252515168620387372061245411590394501381262361357660591775,"line":367,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log","log_context":["UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_nothing_dev","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.66997412221614773869487011266467997625614782764941389305909321698608269368198","seed":66997412221614773869487011266467997625614782764941389305909321698608269368198,"line":327,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log","log_context":["UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode":[{"name":"rom_e2e_sigverify_always_a_bad_b_bad_prod","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_bad_prod.100289219284961125356718945691999206069183095055266254709104441448353632232823","seed":100289219284961125356718945691999206069183095055266254709104441448353632232823,"line":366,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest/run.log","log_context":["UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_bad_prod_end","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.41268379600598006049968574065419670295884797468868315582650078658021019795142","seed":41268379600598006049968574065419670295884797468868315582650078658021019795142,"line":367,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest/run.log","log_context":["UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_bad_rma","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_bad_rma.109987067058024300230191431217626717134732889170616234339427941211085957702201","seed":109987067058024300230191431217626717134732889170616234339427941211085957702201,"line":367,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest/run.log","log_context":["UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_nothing_prod","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.94836870789742848615178018409740916537485423447014552333667354799905007748726","seed":94836870789742848615178018409740916537485423447014552333667354799905007748726,"line":328,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod/latest/run.log","log_context":["UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_nothing_prod_end","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.45559610977640634501705610901202366025154642983143741570853213824308837761285","seed":45559610977640634501705610901202366025154642983143741570853213824308837761285,"line":328,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end/latest/run.log","log_context":["UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_nothing_rma","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.49754298999871874846301479103086374341469224196321422190429154798864119467384","seed":49754298999871874846301479103086374341469224196321422190429154798864119467384,"line":327,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma/latest/run.log","log_context":["UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode":[{"name":"rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0","qual_name":"0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.22369362054210370818449881785218516373831525123117611139188209255142948447207","seed":22369362054210370818449881785218516373831525123117611139188209255142948447207,"line":325,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log","log_context":["UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode":[{"name":"rom_e2e_sigverify_always_a_nothing_b_bad_dev","qual_name":"0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.80057712381436253018136469130125440246263466441749991465209503779359171045964","seed":80057712381436253018136469130125440246263466441749991465209503779359171045964,"line":325,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log","log_context":["UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode":[{"name":"rom_e2e_sigverify_always_a_nothing_b_bad_prod","qual_name":"0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.69509110008924255832881284325993481673418035813669414159793914777534059519685","seed":69509110008924255832881284325993481673418035813669414159793914777534059519685,"line":325,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log","log_context":["UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_sigverify_always_a_nothing_b_bad_prod_end","qual_name":"0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.56222940720471020307283288352908592940367936712684717980102737018464777924242","seed":56222940720471020307283288352908592940367936712684717980102737018464777924242,"line":326,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log","log_context":["UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_sigverify_always_a_nothing_b_bad_rma","qual_name":"0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.48700126464539470779478968584379899880714913874042435179518386686679197070456","seed":48700126464539470779478968584379899880714913874042435179518386686679197070456,"line":325,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log","log_context":["UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *":[{"name":"rom_e2e_keymgr_init_rom_ext_meas","qual_name":"0.rom_e2e_keymgr_init_rom_ext_meas.113568947558872425128757239293774155413587823183304890081180731127729718861677","seed":113568947558872425128757239293774155413587823183304890081180731127729718861677,"line":319,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log","log_context":["UVM_INFO @ 20909.769429 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Offending '$stable(key_data_i)'":[{"name":"rom_keymgr_functest","qual_name":"0.rom_keymgr_functest.72502620713477053958341910831837716700584413043595740322187757400632054943393","seed":72502620713477053958341910831837716700584413043595740322187757400632054943393,"line":327,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_keymgr_functest/latest/run.log","log_context":["UVM_ERROR @ 4522.620970 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M\n","UVM_INFO @ 4522.620970 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}]}},"passed":253,"total":329,"percent":76.89969604863222}