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[`cbf0611`](https://github.com/lowrisc/opentitan/tree/cbf0611ad746e9d6c7ba45219b8e4e9894cd04ab)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-05-26T15:30:30Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/spi_device_1r1w/data/spi_device_testplan.html","stages":{"unmapped":{"testpoints":{"Unmapped":{"tests":{"spi_device_csb_read":{"max_time":0.83,"sim_time":17.87131,"passed":1,"total":1,"percent":100.0},"spi_device_mem_parity":{"max_time":0.71,"sim_time":3.137823,"passed":0,"total":1,"percent":0.0},"spi_device_ram_cfg":{"max_time":0.84,"sim_time":7.71316,"passed":0,"total":1,"percent":0.0},"spi_device_tpm_read_hw_reg":{"max_time":8.76,"sim_time":4361.085861,"passed":1,"total":1,"percent":100.0},"spi_device_tpm_all":{"max_time":12.36,"sim_time":25044.572465999998,"passed":1,"total":1,"percent":100.0},"spi_device_tpm_sts_read":{"max_time":0.76,"sim_time":12.716211,"passed":1,"total":1,"percent":100.0},"spi_device_tpm_rw":{"max_time":1.21,"sim_time":125.666197,"passed":1,"total":1,"percent":100.0},"spi_device_pass_cmd_filtering":{"max_time":11.67,"sim_time":6895.673139,"passed":1,"total":1,"percent":100.0},"spi_device_pass_addr_payload_swap":{"max_time":4.81,"sim_time":3947.604819,"passed":1,"total":1,"percent":100.0},"spi_device_intercept":{"max_time":4.44,"sim_time":6072.383385,"passed":1,"total":1,"percent":100.0},"spi_device_mailbox":{"max_time":6.21,"sim_time":1829.58954,"passed":1,"total":1,"percent":100.0},"spi_device_upload":{"max_time":3.4,"sim_time":259.090302,"passed":1,"total":1,"percent":100.0},"spi_device_cfg_cmd":{"max_time":3.96,"sim_time":1959.278738,"passed":1,"total":1,"percent":100.0},"spi_device_flash_mode":{"max_time":13.8,"sim_time":7919.973161,"passed":1,"total":1,"percent":100.0},"spi_device_flash_mode_ignore_cmds":{"max_time":142.56,"sim_time":31073.344165,"passed":1,"total":1,"percent":100.0},"spi_device_read_buffer_direct":{"max_time":5.13,"sim_time":1302.313979,"passed":1,"total":1,"percent":100.0},"spi_device_flash_all":{"max_time":156.29,"sim_time":362411.285819,"passed":1,"total":1,"percent":100.0},"spi_device_flash_and_tpm":{"max_time":59.06,"sim_time":5017.5146540000005,"passed":1,"total":1,"percent":100.0},"spi_device_flash_and_tpm_min_idle":{"max_time":40.06,"sim_time":58677.421792,"passed":1,"total":1,"percent":100.0},"spi_device_stress_all":{"max_time":1.01,"sim_time":35.353063999999996,"passed":1,"total":1,"percent":100.0},"spi_device_sec_cm":{"max_time":1.4,"sim_time":198.652601,"passed":1,"total":1,"percent":100.0},"spi_device_tl_errors":{"max_time":3.29,"sim_time":160.46001,"passed":1,"total":1,"percent":100.0},"spi_device_tl_intg_err":{"max_time":11.42,"sim_time":1274.897176,"passed":1,"total":1,"percent":100.0},"spi_device_intr_test":{"max_time":0.81,"sim_time":13.552477000000001,"passed":1,"total":1,"percent":100.0},"spi_device_alert_test":{"max_time":0.75,"sim_time":15.998543999999999,"passed":1,"total":1,"percent":100.0},"spi_device_mem_walk":{"max_time":0.98,"sim_time":40.116069,"passed":1,"total":1,"percent":100.0},"spi_device_mem_partial_access":{"max_time":1.26,"sim_time":142.451204,"passed":1,"total":1,"percent":100.0},"spi_device_csr_hw_reset":{"max_time":0.98,"sim_time":18.581176,"passed":1,"total":1,"percent":100.0},"spi_device_csr_rw":{"max_time":1.64,"sim_time":240.91195199999999,"passed":1,"total":1,"percent":100.0},"spi_device_csr_bit_bash":{"max_time":19.02,"sim_time":10415.269947,"passed":1,"total":1,"percent":100.0},"spi_device_csr_aliasing":{"max_time":4.21,"sim_time":209.06754,"passed":1,"total":1,"percent":100.0},"spi_device_same_csr_outstanding":{"max_time":2.48,"sim_time":373.938002,"passed":1,"total":1,"percent":100.0},"spi_device_csr_mem_rw_with_rand_reset":{"max_time":2.02,"sim_time":401.92965000000004,"passed":1,"total":1,"percent":100.0}},"passed":31,"total":33,"percent":93.93939393939394}},"passed":31,"total":33,"percent":93.93939393939394}},"coverage":{"code":{"block":null,"line_statement":98.81,"branch":98.09,"condition_expression":96.13,"toggle":83.54,"fsm":89.36},"assertion":95.26,"functional":64.14},"cov_report_page":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/cov_report/dashboard.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*])":[{"name":"spi_device_mem_parity","qual_name":"0.spi_device_mem_parity.97030645511183236575227669287139489275209524657828789221626901233057758843593","seed":97030645511183236575227669287139489275209524657828789221626901233057758843593,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   2762829 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   2762829 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[987])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]}],"UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*])":[{"name":"spi_device_ram_cfg","qual_name":"0.spi_device_ram_cfg.20173441972693628703121816145366034268479597006070170855850558767499753406638","seed":20173441972693628703121816145366034268479597006070170855850558767499753406638,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log","log_context":["UVM_ERROR @   4848160 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x259ab0 [1001011001101010110000] vs 0x0 [0]) \n","UVM_ERROR @   4859160 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x8c9f0d [100011001001111100001101] vs 0x0 [0]) \n","UVM_ERROR @   4957160 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x86b4db [100001101011010011011011] vs 0x0 [0]) \n","UVM_ERROR @   5041160 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xc7913e [110001111001000100111110] vs 0x0 [0]) \n"]}]}},"passed":31,"total":33,"percent":93.93939393939394}