{"block":{"name":"uart","variant":null,"commit":"cbf0611ad746e9d6c7ba45219b8e4e9894cd04ab","commit_short":"cbf0611","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/cbf0611ad746e9d6c7ba45219b8e4e9894cd04ab","revision_info":"GitHub Revision: [`cbf0611`](https://github.com/lowrisc/opentitan/tree/cbf0611ad746e9d6c7ba45219b8e4e9894cd04ab)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-05-26T15:30:30Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/uart/data/uart_testplan.html","stages":{"unmapped":{"testpoints":{"Unmapped":{"tests":{"uart_smoke":{"max_time":1.6,"sim_time":960.48222,"passed":1,"total":1,"percent":100.0},"uart_tx_rx":{"max_time":86.96,"sim_time":58706.073196000005,"passed":1,"total":1,"percent":100.0},"uart_fifo_full":{"max_time":27.44,"sim_time":71363.693595,"passed":1,"total":1,"percent":100.0},"uart_fifo_overflow":{"max_time":74.19,"sim_time":254274.323819,"passed":1,"total":1,"percent":100.0},"uart_fifo_reset":{"max_time":10.21,"sim_time":29099.9145,"passed":1,"total":1,"percent":100.0},"uart_rx_oversample":{"max_time":14.45,"sim_time":2970.103301,"passed":1,"total":1,"percent":100.0},"uart_intr":{"max_time":5.92,"sim_time":20460.052134,"passed":1,"total":1,"percent":100.0},"uart_noise_filter":{"max_time":15.62,"sim_time":14544.195276,"passed":0,"total":1,"percent":0.0},"uart_rx_start_bit_filter":{"max_time":2.27,"sim_time":4717.331442,"passed":1,"total":1,"percent":100.0},"uart_rx_parity_err":{"max_time":44.49,"sim_time":81830.27448000001,"passed":1,"total":1,"percent":100.0},"uart_tx_ovrd":{"max_time":1.91,"sim_time":2101.362923,"passed":1,"total":1,"percent":100.0},"uart_loopback":{"max_time":8.88,"sim_time":10899.050519999999,"passed":1,"total":1,"percent":100.0},"uart_perf":{"max_time":704.27,"sim_time":22017.107978999997,"passed":1,"total":1,"percent":100.0},"uart_long_xfer_wo_dly":{"max_time":302.26,"sim_time":103357.483024,"passed":1,"total":1,"percent":100.0},"uart_stress_all_with_rand_reset":{"max_time":36.01,"sim_time":4921.364318,"passed":0,"total":1,"percent":0.0},"uart_stress_all":{"max_time":80.67,"sim_time":261892.88727399998,"passed":1,"total":1,"percent":100.0},"uart_sec_cm":{"max_time":0.84,"sim_time":65.670523,"passed":1,"total":1,"percent":100.0},"uart_tl_errors":{"max_time":1.56,"sim_time":393.880256,"passed":1,"total":1,"percent":100.0},"uart_tl_intg_err":{"max_time":1.15,"sim_time":163.775787,"passed":1,"total":1,"percent":100.0},"uart_intr_test":{"max_time":0.63,"sim_time":48.391631000000004,"passed":1,"total":1,"percent":100.0},"uart_alert_test":{"max_time":0.71,"sim_time":11.336093,"passed":1,"total":1,"percent":100.0},"uart_csr_hw_reset":{"max_time":0.67,"sim_time":12.207164,"passed":1,"total":1,"percent":100.0},"uart_csr_rw":{"max_time":0.74,"sim_time":119.873753,"passed":1,"total":1,"percent":100.0},"uart_csr_bit_bash":{"max_time":1.39,"sim_time":257.78322000000003,"passed":1,"total":1,"percent":100.0},"uart_csr_aliasing":{"max_time":0.78,"sim_time":101.61173299999999,"passed":1,"total":1,"percent":100.0},"uart_same_csr_outstanding":{"max_time":0.76,"sim_time":62.522474,"passed":1,"total":1,"percent":100.0},"uart_csr_mem_rw_with_rand_reset":{"max_time":1.01,"sim_time":31.206062000000003,"passed":1,"total":1,"percent":100.0}},"passed":25,"total":27,"percent":92.5925925925926}},"passed":25,"total":27,"percent":92.5925925925926}},"coverage":{"code":{"block":null,"line_statement":98.86,"branch":96.5,"condition_expression":93.23,"toggle":91.32,"fsm":null},"assertion":98.27,"functional":61.08},"cov_report_page":"/nightly/current_run/scratch/master/uart-sim-vcs/cov_report/dashboard.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: *":[{"name":"uart_noise_filter","qual_name":"0.uart_noise_filter.59676225612375073450037241602600831696167359286677226103119649681408547609328","seed":59676225612375073450037241602600831696167359286677226103119649681408547609328,"line":79,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 6652655276 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 6652665276 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (240 [0xf0] vs 255 [0xff]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 6652675276 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 6652685276 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (240 [0xf0] vs 127 [0x7f]) reg name: uart_reg_block.rdata\n"]}],"UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = *":[{"name":"uart_stress_all_with_rand_reset","qual_name":"0.uart_stress_all_with_rand_reset.114859589010482294691541212841812191294190815342045551352609425621656609769043","seed":114859589010482294691541212841812191294190815342045551352609425621656609769043,"line":109,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/0.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 668582560 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 3/449\n","UVM_ERROR @ 695322999 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0\n","UVM_ERROR @ 695333416 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 695406335 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata\n"]}]}},"passed":25,"total":27,"percent":92.5925925925926}