{"block":{"name":"clkmgr","variant":null,"commit":"d967e2f66621cc3035b3ec4e27743a5ae6222efd","commit_short":"d967e2f","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/d967e2f66621cc3035b3ec4e27743a5ae6222efd","revision_info":"GitHub Revision: [`d967e2f`](https://github.com/lowrisc/opentitan/tree/d967e2f66621cc3035b3ec4e27743a5ae6222efd)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-05-27T15:30:30Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/top_earlgrey/ip_autogen/clkmgr/data/clkmgr_testplan.html","stages":{"unmapped":{"testpoints":{"Unmapped":{"tests":{"clkmgr_smoke":{"max_time":0.85,"sim_time":45.107345,"passed":1,"total":1,"percent":100.0},"clkmgr_extclk":{"max_time":0.88,"sim_time":112.453092,"passed":1,"total":1,"percent":100.0},"clkmgr_frequency":{"max_time":3.16,"sim_time":557.8840670000001,"passed":1,"total":1,"percent":100.0},"clkmgr_frequency_timeout":{"max_time":5.52,"sim_time":2490.797048,"passed":1,"total":1,"percent":100.0},"clkmgr_peri":{"max_time":0.8,"sim_time":45.741312,"passed":1,"total":1,"percent":100.0},"clkmgr_trans":{"max_time":0.78,"sim_time":36.054589,"passed":1,"total":1,"percent":100.0},"clkmgr_clk_status":{"max_time":0.79,"sim_time":82.634195,"passed":1,"total":1,"percent":100.0},"clkmgr_idle_intersig_mubi":{"max_time":0.93,"sim_time":47.979651,"passed":1,"total":1,"percent":100.0},"clkmgr_lc_ctrl_intersig_mubi":{"max_time":0.85,"sim_time":42.424529,"passed":1,"total":1,"percent":100.0},"clkmgr_lc_clk_byp_req_intersig_mubi":{"max_time":0.75,"sim_time":48.022477,"passed":1,"total":1,"percent":100.0},"clkmgr_clk_handshake_intersig_mubi":{"max_time":0.83,"sim_time":45.749894999999995,"passed":1,"total":1,"percent":100.0},"clkmgr_div_intersig_mubi":{"max_time":0.9,"sim_time":45.553492,"passed":1,"total":1,"percent":100.0},"clkmgr_regwen":{"max_time":2.04,"sim_time":553.829345,"passed":1,"total":1,"percent":100.0},"clkmgr_shadow_reg_errors":{"max_time":366.33,"sim_time":200000.0,"passed":0,"total":1,"percent":0.0},"clkmgr_shadow_reg_errors_with_csr_rw":{"max_time":497.26,"sim_time":200000.0,"passed":0,"total":1,"percent":0.0},"clkmgr_sec_cm":{"max_time":0.88,"sim_time":34.851142,"passed":0,"total":1,"percent":0.0},"clkmgr_stress_all_with_rand_reset":{"max_time":65.56,"sim_time":19938.834440000002,"passed":1,"total":1,"percent":100.0},"clkmgr_stress_all":{"max_time":34.1,"sim_time":7803.160735,"passed":1,"total":1,"percent":100.0},"clkmgr_tl_errors":{"max_time":1.69,"sim_time":141.133329,"passed":1,"total":1,"percent":100.0},"clkmgr_tl_intg_err":{"max_time":31.76,"sim_time":10115.559967000001,"passed":0,"total":1,"percent":0.0},"clkmgr_alert_test":{"max_time":0.74,"sim_time":42.124829,"passed":1,"total":1,"percent":100.0},"clkmgr_csr_hw_reset":{"max_time":0.86,"sim_time":68.14081200000001,"passed":1,"total":1,"percent":100.0},"clkmgr_csr_rw":{"max_time":0.79,"sim_time":18.476473000000002,"passed":1,"total":1,"percent":100.0},"clkmgr_csr_bit_bash":{"max_time":3.31,"sim_time":325.86373100000003,"passed":1,"total":1,"percent":100.0},"clkmgr_csr_aliasing":{"max_time":1.16,"sim_time":45.950607000000005,"passed":1,"total":1,"percent":100.0},"clkmgr_same_csr_outstanding":{"max_time":0.9,"sim_time":36.631741999999996,"passed":1,"total":1,"percent":100.0},"clkmgr_csr_mem_rw_with_rand_reset":{"max_time":0.9,"sim_time":22.970333,"passed":1,"total":1,"percent":100.0}},"passed":23,"total":27,"percent":85.18518518518519}},"passed":23,"total":27,"percent":85.18518518518519}},"coverage":{"code":{"block":null,"line_statement":98.54,"branch":97.85,"condition_expression":89.59,"toggle":98.71,"fsm":100.0},"assertion":92.94,"functional":84.05},"cov_report_page":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/cov_report/dashboard.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue":[{"name":"clkmgr_shadow_reg_errors","qual_name":"0.clkmgr_shadow_reg_errors.55170826379174035114862866333072034180693902846843259204022338225835533004067","seed":55170826379174035114862866333072034180693902846843259204022338225835533004067,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_shadow_reg_errors/latest/run.log","log_context":["UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"0.clkmgr_shadow_reg_errors_with_csr_rw.96794612791471540666515068806342471451495929484334156437347735979385364011276","seed":96794612791471540666515068806342471451495929484334156437347735979385364011276,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:1047) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles.":[{"name":"clkmgr_sec_cm","qual_name":"0.clkmgr_sec_cm.37550161110449114406468221045878246312018567680414053080807880451815096215992","seed":37550161110449114406468221045878246312018567680414053080807880451815096215992,"line":99,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_sec_cm/latest/run.log","log_context":["UVM_INFO @  34851142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:1077) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault":[{"name":"clkmgr_tl_intg_err","qual_name":"0.clkmgr_tl_intg_err.53963390813728903388011684656946912524949023695905722339244765062400599726745","seed":53963390813728903388011684656946912524949023695905722339244765062400599726745,"line":151,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_INFO @ 10115559967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":23,"total":27,"percent":85.18518518518519}