{"block":{"name":"spi_device","variant":"1r1w","commit":"d967e2f66621cc3035b3ec4e27743a5ae6222efd","commit_short":"d967e2f","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/d967e2f66621cc3035b3ec4e27743a5ae6222efd","revision_info":"GitHub Revision: [`d967e2f`](https://github.com/lowrisc/opentitan/tree/d967e2f66621cc3035b3ec4e27743a5ae6222efd)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-05-27T15:30:30Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/spi_device_1r1w/data/spi_device_testplan.html","stages":{"unmapped":{"testpoints":{"Unmapped":{"tests":{"spi_device_csb_read":{"max_time":0.76,"sim_time":44.423649,"passed":1,"total":1,"percent":100.0},"spi_device_mem_parity":{"max_time":0.72,"sim_time":2.64721,"passed":0,"total":1,"percent":0.0},"spi_device_ram_cfg":{"max_time":0.8,"sim_time":4.219398,"passed":0,"total":1,"percent":0.0},"spi_device_tpm_read_hw_reg":{"max_time":8.1,"sim_time":6265.594661,"passed":1,"total":1,"percent":100.0},"spi_device_tpm_all":{"max_time":37.16,"sim_time":21823.552646,"passed":1,"total":1,"percent":100.0},"spi_device_tpm_sts_read":{"max_time":0.83,"sim_time":47.719052000000005,"passed":1,"total":1,"percent":100.0},"spi_device_tpm_rw":{"max_time":1.76,"sim_time":217.04225399999999,"passed":1,"total":1,"percent":100.0},"spi_device_pass_cmd_filtering":{"max_time":7.66,"sim_time":17807.898135000003,"passed":1,"total":1,"percent":100.0},"spi_device_pass_addr_payload_swap":{"max_time":24.08,"sim_time":11716.588937,"passed":1,"total":1,"percent":100.0},"spi_device_intercept":{"max_time":2.76,"sim_time":122.142031,"passed":1,"total":1,"percent":100.0},"spi_device_mailbox":{"max_time":8.09,"sim_time":1676.379416,"passed":1,"total":1,"percent":100.0},"spi_device_upload":{"max_time":4.03,"sim_time":692.0953149999999,"passed":1,"total":1,"percent":100.0},"spi_device_cfg_cmd":{"max_time":2.13,"sim_time":715.567983,"passed":1,"total":1,"percent":100.0},"spi_device_flash_mode":{"max_time":8.13,"sim_time":13179.304994,"passed":1,"total":1,"percent":100.0},"spi_device_flash_mode_ignore_cmds":{"max_time":58.1,"sim_time":28221.78789,"passed":1,"total":1,"percent":100.0},"spi_device_read_buffer_direct":{"max_time":9.75,"sim_time":11152.630532,"passed":1,"total":1,"percent":100.0},"spi_device_flash_all":{"max_time":97.27,"sim_time":60408.176928,"passed":1,"total":1,"percent":100.0},"spi_device_flash_and_tpm":{"max_time":46.17,"sim_time":14076.877414,"passed":1,"total":1,"percent":100.0},"spi_device_flash_and_tpm_min_idle":{"max_time":257.17,"sim_time":275968.208879,"passed":1,"total":1,"percent":100.0},"spi_device_stress_all":{"max_time":0.9,"sim_time":156.56902100000002,"passed":1,"total":1,"percent":100.0},"spi_device_sec_cm":{"max_time":1.35,"sim_time":94.653676,"passed":1,"total":1,"percent":100.0},"spi_device_tl_errors":{"max_time":1.67,"sim_time":73.69625500000001,"passed":1,"total":1,"percent":100.0},"spi_device_tl_intg_err":{"max_time":4.46,"sim_time":112.918382,"passed":1,"total":1,"percent":100.0},"spi_device_intr_test":{"max_time":0.75,"sim_time":15.002253000000001,"passed":1,"total":1,"percent":100.0},"spi_device_alert_test":{"max_time":0.66,"sim_time":16.679097000000002,"passed":1,"total":1,"percent":100.0},"spi_device_mem_walk":{"max_time":0.67,"sim_time":13.674781999999999,"passed":1,"total":1,"percent":100.0},"spi_device_mem_partial_access":{"max_time":1.54,"sim_time":24.774359,"passed":1,"total":1,"percent":100.0},"spi_device_csr_hw_reset":{"max_time":0.96,"sim_time":18.824279999999998,"passed":1,"total":1,"percent":100.0},"spi_device_csr_rw":{"max_time":1.81,"sim_time":38.793974999999996,"passed":1,"total":1,"percent":100.0},"spi_device_csr_bit_bash":{"max_time":27.74,"sim_time":4130.785771,"passed":1,"total":1,"percent":100.0},"spi_device_csr_aliasing":{"max_time":16.7,"sim_time":7715.296702,"passed":1,"total":1,"percent":100.0},"spi_device_same_csr_outstanding":{"max_time":1.55,"sim_time":65.916792,"passed":1,"total":1,"percent":100.0},"spi_device_csr_mem_rw_with_rand_reset":{"max_time":1.96,"sim_time":78.234216,"passed":1,"total":1,"percent":100.0}},"passed":31,"total":33,"percent":93.93939393939394}},"passed":31,"total":33,"percent":93.93939393939394}},"coverage":{"code":{"block":null,"line_statement":98.86,"branch":98.2,"condition_expression":95.51,"toggle":83.54,"fsm":89.36},"assertion":95.51,"functional":68.35},"cov_report_page":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/cov_report/dashboard.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*])":[{"name":"spi_device_mem_parity","qual_name":"0.spi_device_mem_parity.10438136497618769214465351494586179634177091077422240661753401142166693469635","seed":10438136497618769214465351494586179634177091077422240661753401142166693469635,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   2230550 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   2230550 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[914])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]}],"UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*])":[{"name":"spi_device_ram_cfg","qual_name":"0.spi_device_ram_cfg.62876567580700449422481643054327375477851507002375945934709193691242881558072","seed":62876567580700449422481643054327375477851507002375945934709193691242881558072,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log","log_context":["UVM_ERROR @   1933398 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x41a34a [10000011010001101001010] vs 0x0 [0]) \n","UVM_ERROR @   1996398 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x47096 [1000111000010010110] vs 0x0 [0]) \n","UVM_ERROR @   2011398 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x57a1d0 [10101111010000111010000] vs 0x0 [0]) \n","UVM_ERROR @   2072398 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xaf303a [101011110011000000111010] vs 0x0 [0]) \n"]}]}},"passed":31,"total":33,"percent":93.93939393939394}