{"block":{"name":"uart","variant":null,"commit":"d967e2f66621cc3035b3ec4e27743a5ae6222efd","commit_short":"d967e2f","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/d967e2f66621cc3035b3ec4e27743a5ae6222efd","revision_info":"GitHub Revision: [`d967e2f`](https://github.com/lowrisc/opentitan/tree/d967e2f66621cc3035b3ec4e27743a5ae6222efd)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-05-27T15:30:30Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/uart/data/uart_testplan.html","stages":{"unmapped":{"testpoints":{"Unmapped":{"tests":{"uart_smoke":{"max_time":1.37,"sim_time":494.539365,"passed":1,"total":1,"percent":100.0},"uart_tx_rx":{"max_time":26.34,"sim_time":66317.804814,"passed":1,"total":1,"percent":100.0},"uart_fifo_full":{"max_time":14.5,"sim_time":51859.851774999996,"passed":1,"total":1,"percent":100.0},"uart_fifo_overflow":{"max_time":105.53,"sim_time":86520.34289100001,"passed":1,"total":1,"percent":100.0},"uart_fifo_reset":{"max_time":14.98,"sim_time":10328.911522,"passed":1,"total":1,"percent":100.0},"uart_rx_oversample":{"max_time":11.41,"sim_time":7118.750457,"passed":1,"total":1,"percent":100.0},"uart_intr":{"max_time":73.33,"sim_time":80038.189764,"passed":1,"total":1,"percent":100.0},"uart_noise_filter":{"max_time":2.99,"sim_time":1010.5490420000001,"passed":0,"total":1,"percent":0.0},"uart_rx_start_bit_filter":{"max_time":3.05,"sim_time":1812.3155789999998,"passed":1,"total":1,"percent":100.0},"uart_rx_parity_err":{"max_time":62.91,"sim_time":95806.42369400001,"passed":1,"total":1,"percent":100.0},"uart_tx_ovrd":{"max_time":15.63,"sim_time":6112.906973,"passed":1,"total":1,"percent":100.0},"uart_loopback":{"max_time":4.56,"sim_time":5565.724585,"passed":1,"total":1,"percent":100.0},"uart_perf":{"max_time":76.85,"sim_time":10208.144341,"passed":1,"total":1,"percent":100.0},"uart_long_xfer_wo_dly":{"max_time":540.41,"sim_time":127688.731215,"passed":1,"total":1,"percent":100.0},"uart_stress_all_with_rand_reset":{"max_time":6.69,"sim_time":894.077262,"passed":1,"total":1,"percent":100.0},"uart_stress_all":{"max_time":54.94,"sim_time":93342.34497,"passed":1,"total":1,"percent":100.0},"uart_sec_cm":{"max_time":0.88,"sim_time":116.410244,"passed":1,"total":1,"percent":100.0},"uart_tl_errors":{"max_time":2.68,"sim_time":260.197087,"passed":1,"total":1,"percent":100.0},"uart_tl_intg_err":{"max_time":1.15,"sim_time":76.93124300000001,"passed":1,"total":1,"percent":100.0},"uart_intr_test":{"max_time":0.69,"sim_time":14.771773999999999,"passed":1,"total":1,"percent":100.0},"uart_alert_test":{"max_time":0.83,"sim_time":17.267813999999998,"passed":1,"total":1,"percent":100.0},"uart_csr_hw_reset":{"max_time":0.92,"sim_time":16.059984,"passed":1,"total":1,"percent":100.0},"uart_csr_rw":{"max_time":0.64,"sim_time":15.231399,"passed":1,"total":1,"percent":100.0},"uart_csr_bit_bash":{"max_time":1.59,"sim_time":160.759907,"passed":1,"total":1,"percent":100.0},"uart_csr_aliasing":{"max_time":1.01,"sim_time":37.516116000000004,"passed":1,"total":1,"percent":100.0},"uart_same_csr_outstanding":{"max_time":0.75,"sim_time":22.752119999999998,"passed":1,"total":1,"percent":100.0},"uart_csr_mem_rw_with_rand_reset":{"max_time":0.98,"sim_time":125.14858500000001,"passed":1,"total":1,"percent":100.0}},"passed":26,"total":27,"percent":96.29629629629629}},"passed":26,"total":27,"percent":96.29629629629629}},"coverage":{"code":{"block":null,"line_statement":99.17,"branch":97.44,"condition_expression":95.33,"toggle":91.55,"fsm":null},"assertion":98.85,"functional":51.95},"cov_report_page":"/nightly/current_run/scratch/master/uart-sim-vcs/cov_report/dashboard.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = *":[{"name":"uart_noise_filter","qual_name":"0.uart_noise_filter.96912248476585795092337552240457066541584895231217678879241415882323503557784","seed":96912248476585795092337552240457066541584895231217678879241415882323503557784,"line":74,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @  15359418 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @  24204540 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @  24204540 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 245394444 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]}]}},"passed":26,"total":27,"percent":96.29629629629629}