{"block":{"name":"spi_device","variant":"1r1w","commit":"1d0cf808c91f76f1d0426628dfa14b906434ff05","commit_short":"1d0cf80","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/1d0cf808c91f76f1d0426628dfa14b906434ff05","revision_info":"GitHub Revision: [`1d0cf80`](https://github.com/lowrisc/opentitan/tree/1d0cf808c91f76f1d0426628dfa14b906434ff05)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-05-28T15:30:27Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/spi_device_1r1w/data/spi_device_testplan.html","stages":{"unmapped":{"testpoints":{"Unmapped":{"tests":{"spi_device_csb_read":{"max_time":0.73,"sim_time":13.475727999999998,"passed":1,"total":1,"percent":100.0},"spi_device_mem_parity":{"max_time":0.72,"sim_time":1.8505250000000002,"passed":0,"total":1,"percent":0.0},"spi_device_ram_cfg":{"max_time":0.77,"sim_time":3.578647,"passed":0,"total":1,"percent":0.0},"spi_device_tpm_read_hw_reg":{"max_time":2.42,"sim_time":1986.052308,"passed":1,"total":1,"percent":100.0},"spi_device_tpm_all":{"max_time":14.69,"sim_time":1308.893632,"passed":1,"total":1,"percent":100.0},"spi_device_tpm_sts_read":{"max_time":0.97,"sim_time":123.475829,"passed":1,"total":1,"percent":100.0},"spi_device_tpm_rw":{"max_time":1.85,"sim_time":139.558277,"passed":1,"total":1,"percent":100.0},"spi_device_pass_cmd_filtering":{"max_time":4.06,"sim_time":365.02296,"passed":1,"total":1,"percent":100.0},"spi_device_pass_addr_payload_swap":{"max_time":6.04,"sim_time":1440.3601669999998,"passed":1,"total":1,"percent":100.0},"spi_device_intercept":{"max_time":4.06,"sim_time":3964.636881,"passed":1,"total":1,"percent":100.0},"spi_device_mailbox":{"max_time":23.29,"sim_time":23189.819347,"passed":1,"total":1,"percent":100.0},"spi_device_upload":{"max_time":10.06,"sim_time":15276.241798000001,"passed":1,"total":1,"percent":100.0},"spi_device_cfg_cmd":{"max_time":6.86,"sim_time":4671.710632,"passed":1,"total":1,"percent":100.0},"spi_device_flash_mode":{"max_time":13.82,"sim_time":5050.267935,"passed":1,"total":1,"percent":100.0},"spi_device_flash_mode_ignore_cmds":{"max_time":99.34,"sim_time":64849.43129200001,"passed":1,"total":1,"percent":100.0},"spi_device_read_buffer_direct":{"max_time":3.16,"sim_time":512.512786,"passed":1,"total":1,"percent":100.0},"spi_device_flash_all":{"max_time":172.92,"sim_time":39459.29004,"passed":1,"total":1,"percent":100.0},"spi_device_flash_and_tpm":{"max_time":157.25,"sim_time":150318.43451,"passed":1,"total":1,"percent":100.0},"spi_device_flash_and_tpm_min_idle":{"max_time":67.08,"sim_time":12193.140765,"passed":1,"total":1,"percent":100.0},"spi_device_stress_all":{"max_time":114.39,"sim_time":34788.417953000004,"passed":1,"total":1,"percent":100.0},"spi_device_sec_cm":{"max_time":1.26,"sim_time":92.405817,"passed":1,"total":1,"percent":100.0},"spi_device_tl_errors":{"max_time":1.85,"sim_time":1500.887019,"passed":1,"total":1,"percent":100.0},"spi_device_tl_intg_err":{"max_time":6.0,"sim_time":641.126994,"passed":1,"total":1,"percent":100.0},"spi_device_intr_test":{"max_time":1.07,"sim_time":35.132886,"passed":1,"total":1,"percent":100.0},"spi_device_alert_test":{"max_time":0.87,"sim_time":16.775482,"passed":1,"total":1,"percent":100.0},"spi_device_mem_walk":{"max_time":0.69,"sim_time":34.555343,"passed":1,"total":1,"percent":100.0},"spi_device_mem_partial_access":{"max_time":1.96,"sim_time":235.324756,"passed":1,"total":1,"percent":100.0},"spi_device_csr_hw_reset":{"max_time":1.36,"sim_time":45.88227,"passed":1,"total":1,"percent":100.0},"spi_device_csr_rw":{"max_time":1.78,"sim_time":39.907741,"passed":1,"total":1,"percent":100.0},"spi_device_csr_bit_bash":{"max_time":16.15,"sim_time":368.27274800000004,"passed":1,"total":1,"percent":100.0},"spi_device_csr_aliasing":{"max_time":5.99,"sim_time":429.769495,"passed":1,"total":1,"percent":100.0},"spi_device_same_csr_outstanding":{"max_time":2.11,"sim_time":84.644028,"passed":1,"total":1,"percent":100.0},"spi_device_csr_mem_rw_with_rand_reset":{"max_time":1.7,"sim_time":57.220879000000004,"passed":1,"total":1,"percent":100.0}},"passed":31,"total":33,"percent":93.93939393939394}},"passed":31,"total":33,"percent":93.93939393939394}},"coverage":{"code":{"block":null,"line_statement":98.89,"branch":98.25,"condition_expression":95.97,"toggle":83.54,"fsm":89.36},"assertion":95.39,"functional":74.75},"cov_report_page":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/cov_report/dashboard.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*])":[{"name":"spi_device_mem_parity","qual_name":"0.spi_device_mem_parity.81955246915921545711331734863919100985342622143928999346047653033065888972285","seed":81955246915921545711331734863919100985342622143928999346047653033065888972285,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1483181 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1483181 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[950])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]}],"UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*])":[{"name":"spi_device_ram_cfg","qual_name":"0.spi_device_ram_cfg.31304590387721649359774637808511234630937922014642801331884932228929997758602","seed":31304590387721649359774637808511234630937922014642801331884932228929997758602,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log","log_context":["UVM_ERROR @   1087647 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xcc7127 [110011000111000100100111] vs 0x0 [0]) \n","UVM_ERROR @   1096647 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x7c2494 [11111000010010010010100] vs 0x0 [0]) \n","UVM_ERROR @   1103647 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x194d9b [110010100110110011011] vs 0x0 [0]) \n","UVM_ERROR @   1196647 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3250f2 [1100100101000011110010] vs 0x0 [0]) \n"]}]}},"passed":31,"total":33,"percent":93.93939393939394}