{"block":{"name":"spi_device","variant":"1r1w","commit":"12b260e6aef05e74201b90222a7bb1114c1c1b28","commit_short":"12b260e","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/12b260e6aef05e74201b90222a7bb1114c1c1b28","revision_info":"GitHub Revision: [`12b260e`](https://github.com/lowrisc/opentitan/tree/12b260e6aef05e74201b90222a7bb1114c1c1b28)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-06-01T15:30:27Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/spi_device_1r1w/data/spi_device_testplan.html","stages":{"unmapped":{"testpoints":{"Unmapped":{"tests":{"spi_device_csb_read":{"max_time":0.75,"sim_time":18.108064,"passed":1,"total":1,"percent":100.0},"spi_device_mem_parity":{"max_time":0.7,"sim_time":1.849566,"passed":0,"total":1,"percent":0.0},"spi_device_ram_cfg":{"max_time":0.68,"sim_time":5.890894,"passed":0,"total":1,"percent":0.0},"spi_device_tpm_read_hw_reg":{"max_time":5.39,"sim_time":1774.1950900000002,"passed":1,"total":1,"percent":100.0},"spi_device_tpm_all":{"max_time":11.88,"sim_time":1725.095192,"passed":1,"total":1,"percent":100.0},"spi_device_tpm_sts_read":{"max_time":0.84,"sim_time":116.537209,"passed":1,"total":1,"percent":100.0},"spi_device_tpm_rw":{"max_time":1.13,"sim_time":45.317066,"passed":1,"total":1,"percent":100.0},"spi_device_pass_cmd_filtering":{"max_time":38.96,"sim_time":83676.29156299999,"passed":1,"total":1,"percent":100.0},"spi_device_pass_addr_payload_swap":{"max_time":4.7,"sim_time":1007.3676849999999,"passed":1,"total":1,"percent":100.0},"spi_device_intercept":{"max_time":14.9,"sim_time":10758.264974,"passed":1,"total":1,"percent":100.0},"spi_device_mailbox":{"max_time":40.28,"sim_time":28859.395208,"passed":1,"total":1,"percent":100.0},"spi_device_upload":{"max_time":4.94,"sim_time":3542.1665559999997,"passed":1,"total":1,"percent":100.0},"spi_device_cfg_cmd":{"max_time":1.69,"sim_time":258.567612,"passed":1,"total":1,"percent":100.0},"spi_device_flash_mode":{"max_time":13.76,"sim_time":3493.651146,"passed":1,"total":1,"percent":100.0},"spi_device_flash_mode_ignore_cmds":{"max_time":15.69,"sim_time":2946.9217719999997,"passed":1,"total":1,"percent":100.0},"spi_device_read_buffer_direct":{"max_time":3.47,"sim_time":1120.2098130000002,"passed":1,"total":1,"percent":100.0},"spi_device_flash_all":{"max_time":0.87,"sim_time":103.026235,"passed":1,"total":1,"percent":100.0},"spi_device_flash_and_tpm":{"max_time":327.16,"sim_time":124196.98147900001,"passed":1,"total":1,"percent":100.0},"spi_device_flash_and_tpm_min_idle":{"max_time":23.13,"sim_time":2685.85392,"passed":1,"total":1,"percent":100.0},"spi_device_stress_all":{"max_time":0.94,"sim_time":278.093635,"passed":1,"total":1,"percent":100.0},"spi_device_sec_cm":{"max_time":1.26,"sim_time":226.29852400000001,"passed":1,"total":1,"percent":100.0},"spi_device_tl_errors":{"max_time":1.81,"sim_time":118.976318,"passed":1,"total":1,"percent":100.0},"spi_device_tl_intg_err":{"max_time":6.12,"sim_time":324.26721899999995,"passed":1,"total":1,"percent":100.0},"spi_device_intr_test":{"max_time":0.73,"sim_time":13.574214,"passed":1,"total":1,"percent":100.0},"spi_device_alert_test":{"max_time":0.76,"sim_time":24.493705000000002,"passed":1,"total":1,"percent":100.0},"spi_device_mem_walk":{"max_time":0.68,"sim_time":41.917315,"passed":1,"total":1,"percent":100.0},"spi_device_mem_partial_access":{"max_time":1.52,"sim_time":48.856211,"passed":1,"total":1,"percent":100.0},"spi_device_csr_hw_reset":{"max_time":0.99,"sim_time":36.706331,"passed":1,"total":1,"percent":100.0},"spi_device_csr_rw":{"max_time":1.32,"sim_time":108.623708,"passed":1,"total":1,"percent":100.0},"spi_device_csr_bit_bash":{"max_time":10.14,"sim_time":2163.674952,"passed":1,"total":1,"percent":100.0},"spi_device_csr_aliasing":{"max_time":10.58,"sim_time":747.037181,"passed":1,"total":1,"percent":100.0},"spi_device_same_csr_outstanding":{"max_time":1.5,"sim_time":133.353251,"passed":1,"total":1,"percent":100.0},"spi_device_csr_mem_rw_with_rand_reset":{"max_time":3.0,"sim_time":596.0483780000001,"passed":1,"total":1,"percent":100.0}},"passed":31,"total":33,"percent":93.93939393939394}},"passed":31,"total":33,"percent":93.93939393939394}},"coverage":{"code":{"block":null,"line_statement":98.8,"branch":98.04,"condition_expression":95.13,"toggle":83.54,"fsm":89.36},"assertion":95.39,"functional":59.23},"cov_report_page":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/cov_report/dashboard.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*])":[{"name":"spi_device_mem_parity","qual_name":"0.spi_device_mem_parity.28418411084632806424237635771410508840579604991279927706505550508914407772637","seed":28418411084632806424237635771410508840579604991279927706505550508914407772637,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1255353 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1255353 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[995])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]}],"UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*])":[{"name":"spi_device_ram_cfg","qual_name":"0.spi_device_ram_cfg.4026035560951334317450719051911547471274093967644265106839438872331604566148","seed":4026035560951334317450719051911547471274093967644265106839438872331604566148,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log","log_context":["UVM_ERROR @   3738894 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xb55149 [101101010101000101001001] vs 0x0 [0]) \n","UVM_ERROR @   3778894 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3ca774 [1111001010011101110100] vs 0x0 [0]) \n","UVM_ERROR @   3839894 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x8e73a1 [100011100111001110100001] vs 0x0 [0]) \n","UVM_ERROR @   3934894 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xc2decc [110000101101111011001100] vs 0x0 [0]) \n"]}]}},"passed":31,"total":33,"percent":93.93939393939394}