{"block":{"name":"uart","variant":null,"commit":"12b260e6aef05e74201b90222a7bb1114c1c1b28","commit_short":"12b260e","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/12b260e6aef05e74201b90222a7bb1114c1c1b28","revision_info":"GitHub Revision: [`12b260e`](https://github.com/lowrisc/opentitan/tree/12b260e6aef05e74201b90222a7bb1114c1c1b28)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-06-01T15:30:27Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/uart/data/uart_testplan.html","stages":{"unmapped":{"testpoints":{"Unmapped":{"tests":{"uart_smoke":{"max_time":1.28,"sim_time":549.6143320000001,"passed":1,"total":1,"percent":100.0},"uart_tx_rx":{"max_time":52.03,"sim_time":40601.883729,"passed":1,"total":1,"percent":100.0},"uart_fifo_full":{"max_time":8.01,"sim_time":21033.2691,"passed":1,"total":1,"percent":100.0},"uart_fifo_overflow":{"max_time":33.39,"sim_time":29220.688771,"passed":1,"total":1,"percent":100.0},"uart_fifo_reset":{"max_time":119.04,"sim_time":47070.768726999995,"passed":1,"total":1,"percent":100.0},"uart_rx_oversample":{"max_time":9.28,"sim_time":5029.608821000001,"passed":1,"total":1,"percent":100.0},"uart_intr":{"max_time":26.11,"sim_time":38709.73102000001,"passed":1,"total":1,"percent":100.0},"uart_noise_filter":{"max_time":22.25,"sim_time":27961.054594,"passed":0,"total":1,"percent":0.0},"uart_rx_start_bit_filter":{"max_time":1.89,"sim_time":739.2227290000001,"passed":1,"total":1,"percent":100.0},"uart_rx_parity_err":{"max_time":31.64,"sim_time":70561.774581,"passed":1,"total":1,"percent":100.0},"uart_tx_ovrd":{"max_time":1.39,"sim_time":1474.124684,"passed":1,"total":1,"percent":100.0},"uart_loopback":{"max_time":4.36,"sim_time":10245.123891000001,"passed":1,"total":1,"percent":100.0},"uart_perf":{"max_time":294.22,"sim_time":16542.447467,"passed":1,"total":1,"percent":100.0},"uart_long_xfer_wo_dly":{"max_time":224.28,"sim_time":67974.22325200001,"passed":1,"total":1,"percent":100.0},"uart_stress_all_with_rand_reset":{"max_time":86.94,"sim_time":19161.526719,"passed":1,"total":1,"percent":100.0},"uart_stress_all":{"max_time":353.59,"sim_time":142921.267284,"passed":1,"total":1,"percent":100.0},"uart_sec_cm":{"max_time":1.07,"sim_time":258.428876,"passed":1,"total":1,"percent":100.0},"uart_tl_errors":{"max_time":1.65,"sim_time":265.140815,"passed":1,"total":1,"percent":100.0},"uart_tl_intg_err":{"max_time":1.25,"sim_time":100.194974,"passed":1,"total":1,"percent":100.0},"uart_intr_test":{"max_time":0.6,"sim_time":45.405834000000006,"passed":1,"total":1,"percent":100.0},"uart_alert_test":{"max_time":0.58,"sim_time":14.635348,"passed":1,"total":1,"percent":100.0},"uart_csr_hw_reset":{"max_time":0.71,"sim_time":67.02246400000001,"passed":1,"total":1,"percent":100.0},"uart_csr_rw":{"max_time":0.62,"sim_time":22.320379,"passed":1,"total":1,"percent":100.0},"uart_csr_bit_bash":{"max_time":1.14,"sim_time":135.934928,"passed":1,"total":1,"percent":100.0},"uart_csr_aliasing":{"max_time":0.88,"sim_time":75.90608,"passed":1,"total":1,"percent":100.0},"uart_same_csr_outstanding":{"max_time":0.98,"sim_time":137.818685,"passed":1,"total":1,"percent":100.0},"uart_csr_mem_rw_with_rand_reset":{"max_time":0.66,"sim_time":18.782304,"passed":1,"total":1,"percent":100.0}},"passed":26,"total":27,"percent":96.29629629629629}},"passed":26,"total":27,"percent":96.29629629629629}},"coverage":{"code":{"block":null,"line_statement":99.17,"branch":96.97,"condition_expression":96.15,"toggle":91.55,"fsm":null},"assertion":98.85,"functional":59.19},"cov_report_page":"/nightly/current_run/scratch/master/uart-sim-vcs/cov_report/dashboard.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = *":[{"name":"uart_noise_filter","qual_name":"0.uart_noise_filter.29537406198494698710572375474108818672281497197493679582513953945253906528170","seed":29537406198494698710572375474108818672281497197493679582513953945253906528170,"line":80,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 27938034370 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 27938462938 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 27938871098 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 27939462930 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]}]}},"passed":26,"total":27,"percent":96.29629629629629}