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(uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*])":[{"name":"spi_device_mem_parity","qual_name":"0.spi_device_mem_parity.83550188316143628779656766736561601187657939977570304535188816375865369585089","seed":83550188316143628779656766736561601187657939977570304535188816375865369585089,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1153121 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1153121 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[939])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]}],"UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*])":[{"name":"spi_device_ram_cfg","qual_name":"0.spi_device_ram_cfg.79970619159903919014383155849472380135169701863392030959830694733712993211390","seed":79970619159903919014383155849472380135169701863392030959830694733712993211390,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log","log_context":["UVM_ERROR @   6102628 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x55a5d0 [10101011010010111010000] vs 0x0 [0]) \n","UVM_ERROR @   6195628 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xd1d044 [110100011101000001000100] vs 0x0 [0]) \n","UVM_ERROR @   6198628 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x28126d [1010000001001001101101] vs 0x0 [0]) \n","UVM_ERROR @   6257628 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x5e16ab [10111100001011010101011] vs 0x0 [0]) \n"]}],"UVM_ERROR (spi_device_pass_base_vseq.sv:705) [spi_device_flash_all_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be *":[{"name":"spi_device_flash_all","qual_name":"0.spi_device_flash_all.107806280488645975782453202948845969067731007590557701998130442751021368318438","seed":107806280488645975782453202948845969067731007590557701998130442751021368318438,"line":118,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_flash_all/latest/run.log","log_context":["tl_ul_fuzzy_flash_status_q[i] = 0x832b78\n","tl_ul_fuzzy_flash_status_q[i] = 0x832b78\n","tl_ul_fuzzy_flash_status_q[i] = 0xf482ec\n","tl_ul_fuzzy_flash_status_q[i] = 0x24df78\n"]}],"UVM_ERROR (spi_device_scoreboard.sv:2512) [scoreboard] Check failed item.d_data == `gmv(csr) (* [*] vs * [*]) CSR last_read_addr compare mismatch act * != exp *":[{"name":"spi_device_flash_and_tpm","qual_name":"0.spi_device_flash_and_tpm.113121601849830094006027886777030556401571136850987462742597003562772712071039","seed":113121601849830094006027886777030556401571136850987462742597003562772712071039,"line":99,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_flash_and_tpm/latest/run.log","log_context":["UVM_INFO @ 14795871846 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 4/7\n","UVM_INFO @ 15007142846 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] spi_device_env_pkg::\\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 4/7\n","UVM_INFO @ 15007142846 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] spi_device_env_pkg::\\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 5/7\n","tl_ul_fuzzy_flash_status_q[i] = 0x957852\n"]}]}},"passed":29,"total":33,"percent":87.87878787878788}