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(uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = *":[{"name":"uart_noise_filter","qual_name":"0.uart_noise_filter.38635018649861888916040279434714378583601983710757399252149820623202384974614","seed":38635018649861888916040279434714378583601983710757399252149820623202384974614,"line":75,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 2393656334 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 2394830240 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 2396047624 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 2397438920 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]}],"UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: *":[{"name":"uart_stress_all","qual_name":"0.uart_stress_all.38684910850462385756769063798398788174474095527688955847402369739796344587588","seed":38684910850462385756769063798398788174474095527688955847402369739796344587588,"line":183,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/0.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @ 227737162261 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 227737172570 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (38 [0x26] vs 253 [0xfd]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 227737193188 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 227737203497 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (38 [0x26] vs 254 [0xfe]) reg name: uart_reg_block.rdata\n"]}]}},"passed":25,"total":27,"percent":92.5925925925926}