{"block":{"name":"sram_ctrl","variant":"ret","commit":"9b639d2bc3321697d040cde7b4aea812807d96ab","commit_short":"9b639d2","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/9b639d2bc3321697d040cde7b4aea812807d96ab","revision_info":"GitHub Revision: [`9b639d2`](https://github.com/lowrisc/opentitan/tree/9b639d2bc3321697d040cde7b4aea812807d96ab)"},"tool":{"name":"xcelium","version":"unknown"},"timestamp":"2026-06-25T15:30:31Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/sram_ctrl_ret/data/sram_ctrl_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"sram_ctrl_smoke":{"max_time":1.0,"sim_time":567.5402439999999,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_hw_reset":{"tests":{"sram_ctrl_csr_hw_reset":{"max_time":1.0,"sim_time":37.104592,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_rw":{"tests":{"sram_ctrl_csr_rw":{"max_time":1.0,"sim_time":39.251771999999995,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_bit_bash":{"tests":{"sram_ctrl_csr_bit_bash":{"max_time":3.0,"sim_time":196.70543700000002,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_aliasing":{"tests":{"sram_ctrl_csr_aliasing":{"max_time":1.0,"sim_time":22.760296999999998,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"sram_ctrl_csr_mem_rw_with_rand_reset":{"max_time":1.0,"sim_time":251.10618100000002,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"sram_ctrl_csr_rw":{"max_time":1.0,"sim_time":39.251771999999995,"passed":1,"total":1,"percent":100.0},"sram_ctrl_csr_aliasing":{"max_time":1.0,"sim_time":22.760296999999998,"passed":1,"total":1,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"mem_walk":{"tests":{"sram_ctrl_mem_walk":{"max_time":5.0,"sim_time":4445.38137,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"mem_partial_access":{"tests":{"sram_ctrl_mem_partial_access":{"max_time":4.0,"sim_time":211.47719,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0}},"passed":7,"total":8,"percent":87.5},"V2":{"testpoints":{"multiple_keys":{"tests":{"sram_ctrl_multiple_keys":{"max_time":3.0,"sim_time":364.95500799999996,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"stress_pipeline":{"tests":{"sram_ctrl_stress_pipeline":{"max_time":196.0,"sim_time":4239.703372000001,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"bijection":{"tests":{"sram_ctrl_bijection":{"max_time":4.0,"sim_time":147.19992499999998,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"access_during_key_req":{"tests":{"sram_ctrl_access_during_key_req":{"max_time":11.0,"sim_time":979.2244599999999,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"lc_escalation":{"tests":{"sram_ctrl_lc_escalation":{"max_time":5.0,"sim_time":847.684382,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"executable":{"tests":{"sram_ctrl_executable":{"max_time":6.0,"sim_time":966.424527,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"partial_access":{"tests":{"sram_ctrl_partial_access":{"max_time":2.0,"sim_time":252.190023,"passed":1,"total":1,"percent":100.0},"sram_ctrl_partial_access_b2b":{"max_time":127.0,"sim_time":15447.896756999999,"passed":1,"total":1,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"max_throughput":{"tests":{"sram_ctrl_max_throughput":{"max_time":2.0,"sim_time":51.250269,"passed":0,"total":1,"percent":0.0},"sram_ctrl_throughput_w_partial_write":{"max_time":1.0,"sim_time":27.905855,"passed":0,"total":1,"percent":0.0},"sram_ctrl_throughput_w_readback":{"max_time":2.0,"sim_time":35.536721,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"regwen":{"tests":{"sram_ctrl_regwen":{"max_time":4.0,"sim_time":1043.541814,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"ram_cfg":{"tests":{"sram_ctrl_ram_cfg":{"max_time":2.0,"sim_time":68.239986,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"stress_all":{"tests":{"sram_ctrl_stress_all":{"max_time":23.0,"sim_time":3092.0542680000003,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"alert_test":{"tests":{"sram_ctrl_alert_test":{"max_time":1.0,"sim_time":34.559767,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"sram_ctrl_tl_errors":{"max_time":2.0,"sim_time":144.372712,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"tl_d_illegal_access":{"tests":{"sram_ctrl_tl_errors":{"max_time":2.0,"sim_time":144.372712,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"tl_d_outstanding_access":{"tests":{"sram_ctrl_csr_hw_reset":{"max_time":1.0,"sim_time":37.104592,"passed":1,"total":1,"percent":100.0},"sram_ctrl_csr_rw":{"max_time":1.0,"sim_time":39.251771999999995,"passed":1,"total":1,"percent":100.0},"sram_ctrl_csr_aliasing":{"max_time":1.0,"sim_time":22.760296999999998,"passed":1,"total":1,"percent":100.0},"sram_ctrl_same_csr_outstanding":{"max_time":2.0,"sim_time":25.580553,"passed":1,"total":1,"percent":100.0}},"passed":4,"total":4,"percent":100.0},"tl_d_partial_access":{"tests":{"sram_ctrl_csr_hw_reset":{"max_time":1.0,"sim_time":37.104592,"passed":1,"total":1,"percent":100.0},"sram_ctrl_csr_rw":{"max_time":1.0,"sim_time":39.251771999999995,"passed":1,"total":1,"percent":100.0},"sram_ctrl_csr_aliasing":{"max_time":1.0,"sim_time":22.760296999999998,"passed":1,"total":1,"percent":100.0},"sram_ctrl_same_csr_outstanding":{"max_time":2.0,"sim_time":25.580553,"passed":1,"total":1,"percent":100.0}},"passed":4,"total":4,"percent":100.0}},"passed":17,"total":20,"percent":85.0},"V2S":{"testpoints":{"passthru_mem_tl_intg_err":{"tests":{"sram_ctrl_passthru_mem_tl_intg_err":{"max_time":2.0,"sim_time":796.184662,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"tl_intg_err":{"tests":{"sram_ctrl_sec_cm":{"max_time":2.0,"sim_time":443.90103999999997,"passed":1,"total":1,"percent":100.0},"sram_ctrl_tl_intg_err":{"max_time":2.0,"sim_time":809.35785,"passed":1,"total":1,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"prim_count_check":{"tests":{"sram_ctrl_sec_cm":{"max_time":2.0,"sim_time":443.90103999999997,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"sec_cm_bus_integrity":{"tests":{"sram_ctrl_tl_intg_err":{"max_time":2.0,"sim_time":809.35785,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"sec_cm_ctrl_config_regwen":{"tests":{"sram_ctrl_regwen":{"max_time":4.0,"sim_time":1043.541814,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"sec_cm_readback_config_regwen":{"tests":{"sram_ctrl_regwen":{"max_time":4.0,"sim_time":1043.541814,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"sec_cm_exec_config_regwen":{"tests":{"sram_ctrl_csr_rw":{"max_time":1.0,"sim_time":39.251771999999995,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"sec_cm_exec_config_mubi":{"tests":{"sram_ctrl_executable":{"max_time":6.0,"sim_time":966.424527,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"sec_cm_exec_intersig_mubi":{"tests":{"sram_ctrl_executable":{"max_time":6.0,"sim_time":966.424527,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"sec_cm_lc_hw_debug_en_intersig_mubi":{"tests":{"sram_ctrl_executable":{"max_time":6.0,"sim_time":966.424527,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"sec_cm_lc_escalate_en_intersig_mubi":{"tests":{"sram_ctrl_lc_escalation":{"max_time":5.0,"sim_time":847.684382,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"sec_cm_prim_ram_ctrl_mubi":{"tests":{"sram_ctrl_mubi_enc_err":{"max_time":1.0,"sim_time":35.443914,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"sec_cm_mem_integrity":{"tests":{"sram_ctrl_passthru_mem_tl_intg_err":{"max_time":2.0,"sim_time":796.184662,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"sec_cm_mem_readback":{"tests":{"sram_ctrl_readback_err":{"max_time":1.0,"sim_time":134.016618,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"sec_cm_mem_scramble":{"tests":{"sram_ctrl_smoke":{"max_time":1.0,"sim_time":567.5402439999999,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"sec_cm_addr_scramble":{"tests":{"sram_ctrl_smoke":{"max_time":1.0,"sim_time":567.5402439999999,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"sec_cm_instr_bus_lc_gated":{"tests":{"sram_ctrl_executable":{"max_time":6.0,"sim_time":966.424527,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"sec_cm_ram_tl_lc_gate_fsm_sparse":{"tests":{"sram_ctrl_sec_cm":{"max_time":2.0,"sim_time":443.90103999999997,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"sec_cm_key_global_esc":{"tests":{"sram_ctrl_lc_escalation":{"max_time":5.0,"sim_time":847.684382,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"sec_cm_key_local_esc":{"tests":{"sram_ctrl_sec_cm":{"max_time":2.0,"sim_time":443.90103999999997,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"sec_cm_init_ctr_redun":{"tests":{"sram_ctrl_sec_cm":{"max_time":2.0,"sim_time":443.90103999999997,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"sec_cm_scramble_key_sideload":{"tests":{"sram_ctrl_smoke":{"max_time":1.0,"sim_time":567.5402439999999,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"sec_cm_tlul_fifo_ctr_redun":{"tests":{"sram_ctrl_sec_cm":{"max_time":2.0,"sim_time":443.90103999999997,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"V3":{"testpoints":{"stress_all_with_rand_reset":{"tests":{"sram_ctrl_stress_all_with_rand_reset":{"max_time":40.0,"sim_time":16567.496339,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0}},"coverage":{"code":{"block":93.83,"line_statement":94.99,"branch":89.51,"condition_expression":null,"toggle":82.28,"fsm":66.67},"assertion":97.26,"functional":93.0},"cov_report_page":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cov_report/index.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*])":[{"name":"sram_ctrl_max_throughput","qual_name":"0.sram_ctrl_max_throughput.91601191148517908918066672261755368785862072156564676473075956255314343414044","seed":91601191148517908918066672261755368785862072156564676473075956255314343414044,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_max_throughput/latest/run.log","log_context":["UVM_INFO @  51250269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_partial_write","qual_name":"0.sram_ctrl_throughput_w_partial_write.30974199466907637711949037570991871434957796961486237891016658052445889789694","seed":30974199466907637711949037570991871434957796961486237891016658052445889789694,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_throughput_w_partial_write/latest/run.log","log_context":["UVM_INFO @  27905855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*])":[{"name":"sram_ctrl_throughput_w_readback","qual_name":"0.sram_ctrl_throughput_w_readback.83162180396821792090270290840665002202992454173759431357549792031338547518736","seed":83162180396821792090270290840665002202992454173759431357549792031338547518736,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_throughput_w_readback/latest/run.log","log_context":["UVM_INFO @  35536721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: *":[{"name":"sram_ctrl_csr_mem_rw_with_rand_reset","qual_name":"0.sram_ctrl_csr_mem_rw_with_rand_reset.75390943996449904660555990887324693511635385080342177186339883771628188826700","seed":75390943996449904660555990887324693511635385080342177186339883771628188826700,"line":94,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 251106181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":27,"total":31,"percent":87.09677419354838}