{"block":{"name":"sysrst_ctrl","variant":null,"commit":"dba823ab49fb200ec9d3e991dfb5a83cf1f9c261","commit_short":"dba823a","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/dba823ab49fb200ec9d3e991dfb5a83cf1f9c261","revision_info":"GitHub Revision: [`dba823a`](https://github.com/lowrisc/opentitan/tree/dba823ab49fb200ec9d3e991dfb5a83cf1f9c261)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-07-08T15:30:33Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/sysrst_ctrl/data/sysrst_ctrl_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"sysrst_ctrl_smoke":{"max_time":1.4,"sim_time":2132.229454,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"input_output_inverted":{"tests":{"sysrst_ctrl_in_out_inverted":{"max_time":1.52,"sim_time":2470.6686830000003,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"combo_detect_ec_rst":{"tests":{"sysrst_ctrl_combo_detect_ec_rst":{"max_time":3.21,"sim_time":2144.520171,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"combo_detect_ec_rst_with_pre_cond":{"tests":{"sysrst_ctrl_combo_detect_ec_rst_with_pre_cond":{"max_time":1.42,"sim_time":2565.759469,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_hw_reset":{"tests":{"sysrst_ctrl_csr_hw_reset":{"max_time":7.11,"sim_time":4012.5908990000003,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_rw":{"tests":{"sysrst_ctrl_csr_rw":{"max_time":1.65,"sim_time":2075.284125,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_bit_bash":{"tests":{"sysrst_ctrl_csr_bit_bash":{"max_time":7.67,"sim_time":3057.841737,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_aliasing":{"tests":{"sysrst_ctrl_csr_aliasing":{"max_time":3.87,"sim_time":3337.203068,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"sysrst_ctrl_csr_mem_rw_with_rand_reset":{"max_time":2.56,"sim_time":2047.7075,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"sysrst_ctrl_csr_rw":{"max_time":1.65,"sim_time":2075.284125,"passed":1,"total":1,"percent":100.0},"sysrst_ctrl_csr_aliasing":{"max_time":3.87,"sim_time":3337.203068,"passed":1,"total":1,"percent":100.0}},"passed":2,"total":2,"percent":100.0}},"passed":9,"total":9,"percent":100.0},"V2":{"testpoints":{"combo_detect":{"tests":{"sysrst_ctrl_combo_detect":{"max_time":159.77,"sim_time":95559.974333,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"combo_detect_with_pre_cond":{"tests":{"sysrst_ctrl_combo_detect_with_pre_cond":{"max_time":17.77,"sim_time":113381.94590899999,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"auto_block_key_outputs":{"tests":{"sysrst_ctrl_auto_blk_key_output":{"max_time":2.5,"sim_time":3400.799979,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"keyboard_input_triggered_interrupt":{"tests":{"sysrst_ctrl_edge_detect":{"max_time":1.5,"sim_time":2453.309999,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"pin_output_keyboard_inversion_control":{"tests":{"sysrst_ctrl_pin_override_test":{"max_time":1.8,"sim_time":2529.013429,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"pin_input_value_accessibility":{"tests":{"sysrst_ctrl_pin_access_test":{"max_time":1.54,"sim_time":2168.939717,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"ec_power_on_reset":{"tests":{"sysrst_ctrl_ec_pwr_on_rst":{"max_time":3.26,"sim_time":3281.259234,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"flash_write_protect_output":{"tests":{"sysrst_ctrl_flash_wr_prot_out":{"max_time":5.15,"sim_time":2614.588277,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"ultra_low_power_test":{"tests":{"sysrst_ctrl_ultra_low_pwr":{"max_time":0.93,"sim_time":4921.63585,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"sysrst_ctrl_feature_disable":{"tests":{"sysrst_ctrl_feature_disable":{"max_time":7.53,"sim_time":37381.316119,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"stress_all":{"tests":{"sysrst_ctrl_stress_all":{"max_time":92.62,"sim_time":235294.714526,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"alert_test":{"tests":{"sysrst_ctrl_alert_test":{"max_time":4.54,"sim_time":2010.098975,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"intr_test":{"tests":{"sysrst_ctrl_intr_test":{"max_time":1.43,"sim_time":2032.2206930000002,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"sysrst_ctrl_tl_errors":{"max_time":2.92,"sim_time":2216.6797540000002,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"tl_d_illegal_access":{"tests":{"sysrst_ctrl_tl_errors":{"max_time":2.92,"sim_time":2216.6797540000002,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"tl_d_outstanding_access":{"tests":{"sysrst_ctrl_csr_hw_reset":{"max_time":7.11,"sim_time":4012.5908990000003,"passed":1,"total":1,"percent":100.0},"sysrst_ctrl_csr_rw":{"max_time":1.65,"sim_time":2075.284125,"passed":1,"total":1,"percent":100.0},"sysrst_ctrl_csr_aliasing":{"max_time":3.87,"sim_time":3337.203068,"passed":1,"total":1,"percent":100.0},"sysrst_ctrl_same_csr_outstanding":{"max_time":5.07,"sim_time":4793.463289,"passed":1,"total":1,"percent":100.0}},"passed":4,"total":4,"percent":100.0},"tl_d_partial_access":{"tests":{"sysrst_ctrl_csr_hw_reset":{"max_time":7.11,"sim_time":4012.5908990000003,"passed":1,"total":1,"percent":100.0},"sysrst_ctrl_csr_rw":{"max_time":1.65,"sim_time":2075.284125,"passed":1,"total":1,"percent":100.0},"sysrst_ctrl_csr_aliasing":{"max_time":3.87,"sim_time":3337.203068,"passed":1,"total":1,"percent":100.0},"sysrst_ctrl_same_csr_outstanding":{"max_time":5.07,"sim_time":4793.463289,"passed":1,"total":1,"percent":100.0}},"passed":4,"total":4,"percent":100.0}},"passed":18,"total":18,"percent":100.0},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"sysrst_ctrl_sec_cm":{"max_time":9.01,"sim_time":22061.294469999997,"passed":1,"total":1,"percent":100.0},"sysrst_ctrl_tl_intg_err":{"max_time":7.59,"sim_time":22596.121715999998,"passed":1,"total":1,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"sec_cm_bus_integrity":{"tests":{"sysrst_ctrl_tl_intg_err":{"max_time":7.59,"sim_time":22596.121715999998,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"V3":{"testpoints":{"stress_all_with_rand_reset":{"tests":{"sysrst_ctrl_stress_all_with_rand_reset":{"max_time":8.38,"sim_time":22367.917174,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0}},"coverage":{"code":{"block":null,"line_statement":97.54,"branch":97.52,"condition_expression":95.0,"toggle":100.0,"fsm":75.0},"assertion":94.16,"functional":70.33},"cov_report_page":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/cov_report/dashboard.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) \u0001":[{"name":"sysrst_ctrl_stress_all_with_rand_reset","qual_name":"0.sysrst_ctrl_stress_all_with_rand_reset.67659772997587374148186216170716412489525183207813720436399500273622671417176","seed":67659772997587374148186216170716412489525183207813720436399500273622671417176,"line":731,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 22123111843 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:95) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a L2H transition on lid_open_i\n","UVM_INFO @ 22319741689 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] \n","Issuing reset for run 10/10\n","UVM_INFO @ 22324741689 ps: (cip_base_vseq.sv:1223) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] \n"]}]}},"passed":26,"total":27,"percent":96.29629629629629}