{"block":{"name":"sram_ctrl","variant":"ret","commit":"99fb7bd3b2330a1bda61b1d3382198d0c7fee8d7","commit_short":"99fb7bd","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/99fb7bd3b2330a1bda61b1d3382198d0c7fee8d7","revision_info":"GitHub Revision: [`99fb7bd`](https://github.com/lowrisc/opentitan/tree/99fb7bd3b2330a1bda61b1d3382198d0c7fee8d7)"},"tool":{"name":"xcelium","version":"unknown"},"timestamp":"2026-07-20T15:30:33Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/sram_ctrl_ret/data/sram_ctrl_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"sram_ctrl_smoke":{"max_time":2.0,"sim_time":590.1119,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_hw_reset":{"tests":{"sram_ctrl_csr_hw_reset":{"max_time":1.0,"sim_time":90.266503,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_rw":{"tests":{"sram_ctrl_csr_rw":{"max_time":1.0,"sim_time":27.237142,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_bit_bash":{"tests":{"sram_ctrl_csr_bit_bash":{"max_time":1.0,"sim_time":320.934174,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_aliasing":{"tests":{"sram_ctrl_csr_aliasing":{"max_time":1.0,"sim_time":16.749446,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"sram_ctrl_csr_mem_rw_with_rand_reset":{"max_time":2.0,"sim_time":44.916,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"sram_ctrl_csr_rw":{"max_time":1.0,"sim_time":27.237142,"passed":1,"total":1,"percent":100.0},"sram_ctrl_csr_aliasing":{"max_time":1.0,"sim_time":16.749446,"passed":1,"total":1,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"mem_walk":{"tests":{"sram_ctrl_mem_walk":{"max_time":10.0,"sim_time":9100.120869999999,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"mem_partial_access":{"tests":{"sram_ctrl_mem_partial_access":{"max_time":4.0,"sim_time":393.13309399999997,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0}},"passed":7,"total":8,"percent":87.5},"V2":{"testpoints":{"multiple_keys":{"tests":{"sram_ctrl_multiple_keys":{"max_time":6.0,"sim_time":479.39036300000004,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"stress_pipeline":{"tests":{"sram_ctrl_stress_pipeline":{"max_time":80.0,"sim_time":1801.007503,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"bijection":{"tests":{"sram_ctrl_bijection":{"max_time":6.0,"sim_time":1463.06106,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"access_during_key_req":{"tests":{"sram_ctrl_access_during_key_req":{"max_time":16.0,"sim_time":2478.333404,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"lc_escalation":{"tests":{"sram_ctrl_lc_escalation":{"max_time":7.0,"sim_time":1364.805165,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"executable":{"tests":{"sram_ctrl_executable":{"max_time":3.0,"sim_time":972.6445239999999,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"partial_access":{"tests":{"sram_ctrl_partial_access":{"max_time":2.0,"sim_time":81.437818,"passed":1,"total":1,"percent":100.0},"sram_ctrl_partial_access_b2b":{"max_time":233.0,"sim_time":19939.103182,"passed":1,"total":1,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"max_throughput":{"tests":{"sram_ctrl_max_throughput":{"max_time":2.0,"sim_time":27.610755,"passed":0,"total":1,"percent":0.0},"sram_ctrl_throughput_w_partial_write":{"max_time":1.0,"sim_time":25.970451,"passed":0,"total":1,"percent":0.0},"sram_ctrl_throughput_w_readback":{"max_time":2.0,"sim_time":33.92498200000001,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"regwen":{"tests":{"sram_ctrl_regwen":{"max_time":6.0,"sim_time":468.051755,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"ram_cfg":{"tests":{"sram_ctrl_ram_cfg":{"max_time":1.0,"sim_time":30.441620999999998,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"stress_all":{"tests":{"sram_ctrl_stress_all":{"max_time":13.0,"sim_time":920.885919,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"alert_test":{"tests":{"sram_ctrl_alert_test":{"max_time":2.0,"sim_time":14.878906,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"sram_ctrl_tl_errors":{"max_time":3.0,"sim_time":283.965773,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"tl_d_illegal_access":{"tests":{"sram_ctrl_tl_errors":{"max_time":3.0,"sim_time":283.965773,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"tl_d_outstanding_access":{"tests":{"sram_ctrl_csr_hw_reset":{"max_time":1.0,"sim_time":90.266503,"passed":1,"total":1,"percent":100.0},"sram_ctrl_csr_rw":{"max_time":1.0,"sim_time":27.237142,"passed":1,"total":1,"percent":100.0},"sram_ctrl_csr_aliasing":{"max_time":1.0,"sim_time":16.749446,"passed":1,"total":1,"percent":100.0},"sram_ctrl_same_csr_outstanding":{"max_time":1.0,"sim_time":65.125287,"passed":1,"total":1,"percent":100.0}},"passed":4,"total":4,"percent":100.0},"tl_d_partial_access":{"tests":{"sram_ctrl_csr_hw_reset":{"max_time":1.0,"sim_time":90.266503,"passed":1,"total":1,"percent":100.0},"sram_ctrl_csr_rw":{"max_time":1.0,"sim_time":27.237142,"passed":1,"total":1,"percent":100.0},"sram_ctrl_csr_aliasing":{"max_time":1.0,"sim_time":16.749446,"passed":1,"total":1,"percent":100.0},"sram_ctrl_same_csr_outstanding":{"max_time":1.0,"sim_time":65.125287,"passed":1,"total":1,"percent":100.0}},"passed":4,"total":4,"percent":100.0}},"passed":17,"total":20,"percent":85.0},"V2S":{"testpoints":{"passthru_mem_tl_intg_err":{"tests":{"sram_ctrl_passthru_mem_tl_intg_err":{"max_time":2.0,"sim_time":628.345472,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"tl_intg_err":{"tests":{"sram_ctrl_sec_cm":{"max_time":5.0,"sim_time":485.104042,"passed":1,"total":1,"percent":100.0},"sram_ctrl_tl_intg_err":{"max_time":2.0,"sim_time":156.666823,"passed":1,"total":1,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"prim_count_check":{"tests":{"sram_ctrl_sec_cm":{"max_time":5.0,"sim_time":485.104042,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"sec_cm_bus_integrity":{"tests":{"sram_ctrl_tl_intg_err":{"max_time":2.0,"sim_time":156.666823,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"sec_cm_ctrl_config_regwen":{"tests":{"sram_ctrl_regwen":{"max_time":6.0,"sim_time":468.051755,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"sec_cm_readback_config_regwen":{"tests":{"sram_ctrl_regwen":{"max_time":6.0,"sim_time":468.051755,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"sec_cm_exec_config_regwen":{"tests":{"sram_ctrl_csr_rw":{"max_time":1.0,"sim_time":27.237142,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"sec_cm_exec_config_mubi":{"tests":{"sram_ctrl_executable":{"max_time":3.0,"sim_time":972.6445239999999,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"sec_cm_exec_intersig_mubi":{"tests":{"sram_ctrl_executable":{"max_time":3.0,"sim_time":972.6445239999999,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"sec_cm_lc_hw_debug_en_intersig_mubi":{"tests":{"sram_ctrl_executable":{"max_time":3.0,"sim_time":972.6445239999999,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"sec_cm_lc_escalate_en_intersig_mubi":{"tests":{"sram_ctrl_lc_escalation":{"max_time":7.0,"sim_time":1364.805165,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"sec_cm_prim_ram_ctrl_mubi":{"tests":{"sram_ctrl_mubi_enc_err":{"max_time":2.0,"sim_time":42.08435,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"sec_cm_mem_integrity":{"tests":{"sram_ctrl_passthru_mem_tl_intg_err":{"max_time":2.0,"sim_time":628.345472,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"sec_cm_mem_readback":{"tests":{"sram_ctrl_readback_err":{"max_time":2.0,"sim_time":238.72785000000002,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"sec_cm_mem_scramble":{"tests":{"sram_ctrl_smoke":{"max_time":2.0,"sim_time":590.1119,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"sec_cm_addr_scramble":{"tests":{"sram_ctrl_smoke":{"max_time":2.0,"sim_time":590.1119,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"sec_cm_instr_bus_lc_gated":{"tests":{"sram_ctrl_executable":{"max_time":3.0,"sim_time":972.6445239999999,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"sec_cm_ram_tl_lc_gate_fsm_sparse":{"tests":{"sram_ctrl_sec_cm":{"max_time":5.0,"sim_time":485.104042,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"sec_cm_key_global_esc":{"tests":{"sram_ctrl_lc_escalation":{"max_time":7.0,"sim_time":1364.805165,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"sec_cm_key_local_esc":{"tests":{"sram_ctrl_sec_cm":{"max_time":5.0,"sim_time":485.104042,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"sec_cm_init_ctr_redun":{"tests":{"sram_ctrl_sec_cm":{"max_time":5.0,"sim_time":485.104042,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"sec_cm_scramble_key_sideload":{"tests":{"sram_ctrl_smoke":{"max_time":2.0,"sim_time":590.1119,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"sec_cm_tlul_fifo_ctr_redun":{"tests":{"sram_ctrl_sec_cm":{"max_time":5.0,"sim_time":485.104042,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0}},"passed":9,"total":10,"percent":90.0},"V3":{"testpoints":{"stress_all_with_rand_reset":{"tests":{"sram_ctrl_stress_all_with_rand_reset":{"max_time":19.0,"sim_time":1051.594841,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0}},"coverage":{"code":{"block":93.69,"line_statement":94.91,"branch":89.2,"condition_expression":null,"toggle":78.32,"fsm":66.67},"assertion":97.81,"functional":94.4},"cov_report_page":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cov_report/index.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*])":[{"name":"sram_ctrl_max_throughput","qual_name":"0.sram_ctrl_max_throughput.56829608710959702220095656195841507163821428221436235773202878651987185752327","seed":56829608710959702220095656195841507163821428221436235773202878651987185752327,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_max_throughput/latest/run.log","log_context":["UVM_INFO @  27610755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_partial_write","qual_name":"0.sram_ctrl_throughput_w_partial_write.53198590676768969137103178212143439349149297561583100049031705654762914873803","seed":53198590676768969137103178212143439349149297561583100049031705654762914873803,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_throughput_w_partial_write/latest/run.log","log_context":["UVM_INFO @  25970451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*])":[{"name":"sram_ctrl_throughput_w_readback","qual_name":"0.sram_ctrl_throughput_w_readback.89257713839241800814554066957654798629755031223299436124908115203272004430833","seed":89257713839241800814554066957654798629755031223299436124908115203272004430833,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_throughput_w_readback/latest/run.log","log_context":["UVM_INFO @  33924982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_scoreboard.sv:582) scoreboard [scoreboard] On interface sram_ctrl_prim_reg_block, item had unexpected d_error value(predicted *, but saw *).":[{"name":"sram_ctrl_mubi_enc_err","qual_name":"0.sram_ctrl_mubi_enc_err.18493479553012119451395177124163478616782036773267641874062259182762019562928","seed":18493479553012119451395177124163478616782036773267641874062259182762019562928,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_mubi_enc_err/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@15269) { a_addr: 'ha85a9fc4  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h83  a_opcode: 'h4  a_user: 'h2642a  d_param: 'h0  d_source: 'h83  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h1  d_error: 'h1  d_sink: 'h0  d_user: 'heaa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{}.\n","UVM_INFO @  42084350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]}],"UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: *":[{"name":"sram_ctrl_csr_mem_rw_with_rand_reset","qual_name":"0.sram_ctrl_csr_mem_rw_with_rand_reset.56267780444528756266656754649190069818596029088587179013648068543246595867731","seed":56267780444528756266656754649190069818596029088587179013648068543246595867731,"line":88,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_INFO @  44916000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":26,"total":31,"percent":83.87096774193549}