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visibility to that name\n"]}],"UVM_ERROR (spi_device_ram_cfg_vseq.sv:28) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*])":[{"name":"spi_device_ram_cfg","qual_name":"0.spi_device_ram_cfg.82960680265050895469102870150179532010153176826816893746612994574699062191994","seed":82960680265050895469102870150179532010153176826816893746612994574699062191994,"line":81,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log","log_context":["UVM_ERROR @   4788255 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x270 [1001110000] vs 0x0 [0]) \n","UVM_ERROR @   4859255 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x47 [1000111] vs 0x0 [0]) \n","UVM_ERROR @   4948255 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x302 [1100000010] vs 0x0 [0]) \n","UVM_ERROR @   5029255 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2bb [1010111011] vs 0x0 [0]) \n"]}],"UVM_ERROR (spi_device_scoreboard.sv:2512) [scoreboard] Check failed item.d_data == `gmv(csr) (* [*] vs * [*]) CSR last_read_addr compare mismatch act * != exp *":[{"name":"spi_device_flash_all","qual_name":"0.spi_device_flash_all.6502137326057672770296748045505439651428826463185098811022885123714639048611","seed":6502137326057672770296748045505439651428826463185098811022885123714639048611,"line":84,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_flash_all/latest/run.log","log_context":["UVM_INFO @ 4386643839 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] spi_device_env_pkg::\\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 1/10\n","UVM_INFO @ 4386643839 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] spi_device_env_pkg::\\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 2/10\n","tl_ul_fuzzy_flash_status_q[i] = 0x243d8c\n","tl_ul_fuzzy_flash_status_q[i] = 0x220158\n"]},{"name":"spi_device_flash_and_tpm_min_idle","qual_name":"0.spi_device_flash_and_tpm_min_idle.106706497368740089330308860097652767424424632019277997565455315624886052901811","seed":106706497368740089330308860097652767424424632019277997565455315624886052901811,"line":94,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_flash_and_tpm_min_idle/latest/run.log","log_context":["UVM_INFO @ 1613715453 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] spi_device_env_pkg::\\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 2/6\n","UVM_INFO @ 1613715453 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] spi_device_env_pkg::\\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 3/6\n","tl_ul_fuzzy_flash_status_q[i] = 0xb30ac6\n","tl_ul_fuzzy_flash_status_q[i] = 0x64172a\n"]}]}},"passed":29,"total":33,"percent":87.87878787878788}