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HwReq))'":[{"name":"chip_sw_pwrmgr_random_sleep_all_reset_reqs","qual_name":"0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.54195357883533702506988683897661272110157081131610041439884020267193688693476","seed":54195357883533702506988683897661272110157081131610041439884020267193688693476,"line":347,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest/run.log","log_context":["UVM_ERROR @ 13380.947000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 13380.947000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_deep_sleep_all_reset_reqs","qual_name":"0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2226865821342214278956269763501114330904099153959318490072958142187323003105","seed":2226865821342214278956269763501114330904099153959318490072958142187323003105,"line":317,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest/run.log","log_context":["UVM_ERROR @ 6068.878500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 6068.878500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_deep_sleep_por_reset","qual_name":"0.chip_sw_pwrmgr_deep_sleep_por_reset.17935891964208177710346809450577745576739603767496801009427376525045621900209","seed":17935891964208177710346809450577745576739603767496801009427376525045621900209,"line":328,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest/run.log","log_context":["UVM_ERROR @ 7893.069000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 7893.069000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_random_sleep_power_glitch_reset","qual_name":"0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.28892808153123633573184152061231935103840950781234521660888431122370378298982","seed":28892808153123633573184152061231935103840950781234521660888431122370378298982,"line":345,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/run.log","log_context":["UVM_ERROR @ 11842.943000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 11842.943000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_aon_timer_wdog_bite_reset","qual_name":"0.chip_sw_aon_timer_wdog_bite_reset.23162074405543596588596318286050699921723017915642323806830633958838355858139","seed":23162074405543596588596318286050699921723017915642323806830633958838355858139,"line":322,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log","log_context":["UVM_ERROR @ 9534.711000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 9534.711000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))'":[{"name":"chip_sw_pwrmgr_sleep_power_glitch_reset","qual_name":"0.chip_sw_pwrmgr_sleep_power_glitch_reset.99871537928935692600887770410366745980530883776705525375039620711957348997919","seed":99871537928935692600887770410366745980530883776705525375039620711957348997919,"line":316,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_power_glitch_reset/latest/run.log","log_context":["UVM_ERROR @ 4080.208720 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A\n","UVM_INFO @ 4080.208720 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns":[{"name":"chip_sw_adc_ctrl_sleep_debug_cable_wakeup","qual_name":"0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.82327558741272164271544527103006166246490059048820939088801713473300535242918","seed":82327558741272164271544527103006166246490059048820939088801713473300535242918,"line":335,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log","log_context":["\n","UVM_INFO @ 35749.173737 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:351)] CHECK-fail: Expect alert *!":[{"name":"chip_sw_alert_test","qual_name":"0.chip_sw_alert_test.22442734247779968439018870062713889715919104630559509618187693174555546409204","seed":22442734247779968439018870062713889715919104630559509618187693174555546409204,"line":310,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log","log_context":["UVM_INFO @ 4410.985708 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)":[{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"0.chip_sw_alert_handler_lpg_sleep_mode_alerts.114484407387820244569409260597550790407370154458402025671570756971385557399071","seed":114484407387820244569409260597550790407370154458402025671570756971385557399071,"line":311,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3565.209800 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Job timed out after * minutes":[{"name":"chip_sw_alert_handler_lpg_sleep_mode_pings","qual_name":"0.chip_sw_alert_handler_lpg_sleep_mode_pings.51222313795556282053909853818571027626484420725596756559114534000544122024180","seed":51222313795556282053909853818571027626484420725596756559114534000544122024180,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log","log_context":[]}],"UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns":[{"name":"chip_sw_hmac_multistream","qual_name":"0.chip_sw_hmac_multistream.35611516948129001803292393482302259904054174316658340674053479756429252503804","seed":35611516948129001803292393482302259904054174316658340674053479756429252503804,"line":357,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_multistream/latest/run.log","log_context":["\n","UVM_INFO @ 12018.473483 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_keymgr_sideload_otbn","qual_name":"0.chip_sw_keymgr_sideload_otbn.47439691942144635038255747644398743714123090438201149731280572035352369445836","seed":47439691942144635038255747644398743714123090438201149731280572035352369445836,"line":339,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_sideload_otbn/latest/run.log","log_context":["\n","UVM_INFO @ 20026.663846 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR @ * us: (cip_base_scoreboard.sv:615) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *).":[{"name":"chip_tl_errors","qual_name":"0.chip_tl_errors.79792012970629203142011286690600767406366809455961638373020919939635514424174","seed":79792012970629203142011286690600767406366809455961638373020919939635514424174,"line":220,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@34625) { a_addr: 'h104d8  a_data: 'ha09a856e  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h28  a_opcode: 'h4  a_user: 'h1bdbd  d_param: 'h0  d_source: 'h28  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 3032.807130 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected":[{"name":"chip_sw_clkmgr_jitter_frequency","qual_name":"0.chip_sw_clkmgr_jitter_frequency.114085543353638098946980614108929808948043015666904173396857128211586399860364","seed":114085543353638098946980614108929808948043015666904173396857128211586399860364,"line":346,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_jitter_frequency/latest/run.log","log_context":["UVM_INFO @ 4453.474363 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:78)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for !get_wakeup_status()":[{"name":"chip_sw_pwrmgr_lowpower_cancel","qual_name":"0.chip_sw_pwrmgr_lowpower_cancel.30683711450203703610066209837851826837136794014726535636986668138219122079174","seed":30683711450203703610066209837851826837136794014726535636986668138219122079174,"line":314,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_lowpower_cancel/latest/run.log","log_context":["UVM_INFO @ 4886.656245 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']":[{"name":"chip_sw_pwrmgr_sleep_wake_5_bug","qual_name":"0.chip_sw_pwrmgr_sleep_wake_5_bug.35865269771473694283624029077463982313251447083059926996497965774122246168891","seed":35865269771473694283624029077463982313251447083059926996497965774122246168891,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_self_hash","qual_name":"0.rom_e2e_self_hash.45529265425483698861024153573599768466059174155809357509178699778909590509880","seed":45529265425483698861024153573599768466059174155809357509178699778909590509880,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log","log_context":["Another command (pid=574051) is running. Waiting for it to complete on the server (server_pid=262655)...\n","Another command (pid=582792) is running. Waiting for it to complete on the server (server_pid=262655)...\n","Another command (pid=520792) is running. Waiting for it to complete on the server (server_pid=262655)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_sensor_ctrl_deep_sleep_wake_up_sim_dv(sw/device/tests/pwrmgr_sensor_ctrl_deep_sleep_wake_up.c:120)] CHECK-STATUS-fail: *":[{"name":"chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up","qual_name":"0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.106730928383925073149159915773526425364246440774907772153939035087338886011822","seed":106730928383925073149159915773526425364246440774907772153939035087338886011822,"line":319,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest/run.log","log_context":["UVM_INFO @ 7289.786669 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Error-[NOA] Null object access":[{"name":"chip_sw_rv_dm_ndm_reset_req_when_cpu_halted","qual_name":"0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.80963952473528555959177060882085787220077817121890042624920467989516000629107","seed":80963952473528555959177060882085787220077817121890042624920467989516000629107,"line":330,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"rom_e2e_jtag_debug_test_unlocked0","qual_name":"0.rom_e2e_jtag_debug_test_unlocked0.102777553355278409466498407169071249908144723371783313320854809502930956925890","seed":102777553355278409466498407169071249908144723371783313320854809502930956925890,"line":355,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"rom_e2e_jtag_debug_dev","qual_name":"0.rom_e2e_jtag_debug_dev.110121778255508914441263741112994355504184607661757672091844576303868902730218","seed":110121778255508914441263741112994355504184607661757672091844576303868902730218,"line":322,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"rom_e2e_jtag_debug_rma","qual_name":"0.rom_e2e_jtag_debug_rma.84936200716948653273761050246805421203896128024433160646576293332259694655470","seed":84936200716948653273761050246805421203896128024433160646576293332259694655470,"line":322,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"rom_e2e_jtag_inject_test_unlocked0","qual_name":"0.rom_e2e_jtag_inject_test_unlocked0.85764638877950539327646830657555465283036264693110717940512236269243405135323","seed":85764638877950539327646830657555465283036264693110717940512236269243405135323,"line":306,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_test_unlocked0/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"rom_e2e_jtag_inject_dev","qual_name":"0.rom_e2e_jtag_inject_dev.22367853177429373159149554742585939484604404416096223979467120695306375131269","seed":22367853177429373159149554742585939484604404416096223979467120695306375131269,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_dev/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"rom_e2e_jtag_inject_rma","qual_name":"0.rom_e2e_jtag_inject_rma.113898696734370527824425249998044469009606768398602534678835390309695204210608","seed":113898696734370527824425249998044469009606768398602534678835390309695204210608,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_rma/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]}],"UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:93) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to wakeup from deep sleep.":[{"name":"chip_sw_rv_dm_access_after_wakeup","qual_name":"0.chip_sw_rv_dm_access_after_wakeup.60527460147231900419928832681375345614992487481452431193869362779492400094396","seed":60527460147231900419928832681375345614992487481452431193869362779492400094396,"line":332,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_access_after_wakeup/latest/run.log","log_context":["UVM_INFO @ 14498.622330 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Offending '(rv_jtag_o == '0)'":[{"name":"chip_sw_rv_dm_access_after_escalation_reset","qual_name":"0.chip_sw_rv_dm_access_after_escalation_reset.94354191687258448330607071147423128805417935541416897124720065179276224243044","seed":94354191687258448330607071147423128805417935541416897124720065179276224243044,"line":314,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_access_after_escalation_reset/latest/run.log","log_context":["UVM_ERROR @ 3287.782120 us: (pinmux_strap_sampling.sv:516) [ASSERT FAILED] RvTapOff1_A\n","UVM_INFO @ 3287.782120 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR @ * us: (cip_base_vseq.sv:660) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch":[{"name":"chip_rv_dm_lc_disabled","qual_name":"0.chip_rv_dm_lc_disabled.16061242977384087278435584241890831009174482662151578778394827622971074335213","seed":16061242977384087278435584241890831009174482662151578778394827622971074335213,"line":240,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log","log_context":["UVM_INFO @ 7711.524275 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (chip_sw_power_idle_load_vseq.sv:24) [chip_sw_power_idle_load_vseq] timeout waiting for SW sync GPIO (*)":[{"name":"chip_sw_power_idle_load","qual_name":"0.chip_sw_power_idle_load.70942499915711979353713587959395123544374473364870063349882562673067886985934","seed":70942499915711979353713587959395123544374473364870063349882562673067886985934,"line":321,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log","log_context":["UVM_INFO @ 15191.624256 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (chip_sw_power_sleep_load_vseq.sv:47) [chip_sw_power_sleep_load_vseq] timeout waiting for SW sync GPIO (*)":[{"name":"chip_sw_power_sleep_load","qual_name":"0.chip_sw_power_sleep_load.20792296592071252840694696019804338660498480293277205029359145951150162707723","seed":20792296592071252840694696019804338660498480293277205029359145951150162707723,"line":332,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log","log_context":["UVM_INFO @ 15310.161130 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *":[{"name":"chip_sw_ast_clk_rst_inputs","qual_name":"0.chip_sw_ast_clk_rst_inputs.88068293187086814776944253952656995696486111790373463415661231922583140087467","seed":88068293187086814776944253952656995696486111790373463415661231922583140087467,"line":330,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log","log_context":["UVM_INFO @ 10529.323334 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (csr_utils_pkg.sv:619) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_*.opcode (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1)":[{"name":"ate_bootstrap_flash_erase","qual_name":"0.ate_bootstrap_flash_erase.112741309032675089776303213369662506608696127710368543523488623244386741745597","seed":112741309032675089776303213369662506608696127710368543523488623244386741745597,"line":275,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.ate_bootstrap_flash_erase/latest/run.log","log_context":["UVM_INFO @ 10010.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Offending '$stable(key_data_i)'":[{"name":"rom_keymgr_functest","qual_name":"0.rom_keymgr_functest.70934854394062809042462882716772223197558628489814380697874152611914449325569","seed":70934854394062809042462882716772223197558628489814380697874152611914449325569,"line":330,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_keymgr_functest/latest/run.log","log_context":["UVM_ERROR @ 6217.170094 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M\n","UVM_INFO @ 6217.170094 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}]}},"passed":284,"total":328,"percent":86.58536585365853}