{"block":{"name":"rram_ctrl","variant":null,"commit":"0de30530ed1783fe9e9884b6499a8cc4b7cd3f8b","commit_short":"0de3053","dirty":false,"branch":"master","url":"https://github.com/lowRISC/opentitan/tree/0de30530ed1783fe9e9884b6499a8cc4b7cd3f8b","revision_info":"GitHub Revision: [`0de3053`](https://github.com/lowrisc/opentitan/tree/0de30530ed1783fe9e9884b6499a8cc4b7cd3f8b)"},"tool":{"name":"xcelium","version":"24.03-s007"},"timestamp":"2026-09-14T17:05:42Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/rram_ctrl/data/rram_ctrl_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"rram_ctrl_smoke":{"max_time":3.0,"sim_time":1009.0466759999998,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_hw_reset":{"tests":{"rram_ctrl_csr_hw_reset":{"max_time":3.0,"sim_time":1216.9115900000002,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_rw":{"tests":{"rram_ctrl_csr_rw":{"max_time":2.0,"sim_time":294.303224,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_bit_bash":{"tests":{"rram_ctrl_csr_bit_bash":{"max_time":13.0,"sim_time":3391.4649139999997,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_aliasing":{"tests":{"rram_ctrl_csr_aliasing":{"max_time":3.0,"sim_time":267.77596500000004,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"rram_ctrl_csr_mem_rw_with_rand_reset":{"max_time":2.0,"sim_time":143.67044399999997,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"rram_ctrl_csr_rw":{"max_time":2.0,"sim_time":294.303224,"passed":1,"total":1,"percent":100.0},"rram_ctrl_csr_aliasing":{"max_time":3.0,"sim_time":267.77596500000004,"passed":1,"total":1,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"mem_walk":{"tests":{"rram_ctrl_mem_walk":{"max_time":2.0,"sim_time":422.922204,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"mem_partial_access":{"tests":{"rram_ctrl_mem_partial_access":{"max_time":3.0,"sim_time":233.06061,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0}},"passed":8,"total":8,"percent":100.0},"V2":{"testpoints":{"intr_test":{"tests":{"rram_ctrl_intr_test":{"max_time":2.0,"sim_time":534.130088,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"alert_test":{"tests":{"rram_ctrl_alert_test":{"max_time":5.0,"sim_time":162.82157899999999,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"rram_ctrl_tl_errors":{"max_time":5.0,"sim_time":155.27606400000002,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"tl_d_illegal_access":{"tests":{"rram_ctrl_tl_errors":{"max_time":5.0,"sim_time":155.27606400000002,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"tl_d_outstanding_access":{"tests":{"rram_ctrl_csr_hw_reset":{"max_time":3.0,"sim_time":1216.9115900000002,"passed":1,"total":1,"percent":100.0},"rram_ctrl_csr_rw":{"max_time":2.0,"sim_time":294.303224,"passed":1,"total":1,"percent":100.0},"rram_ctrl_csr_aliasing":{"max_time":3.0,"sim_time":267.77596500000004,"passed":1,"total":1,"percent":100.0},"rram_ctrl_same_csr_outstanding":{"max_time":3.0,"sim_time":1525.1658149999998,"passed":1,"total":1,"percent":100.0}},"passed":4,"total":4,"percent":100.0},"tl_d_partial_access":{"tests":{"rram_ctrl_csr_hw_reset":{"max_time":3.0,"sim_time":1216.9115900000002,"passed":1,"total":1,"percent":100.0},"rram_ctrl_csr_rw":{"max_time":2.0,"sim_time":294.303224,"passed":1,"total":1,"percent":100.0},"rram_ctrl_csr_aliasing":{"max_time":3.0,"sim_time":267.77596500000004,"passed":1,"total":1,"percent":100.0},"rram_ctrl_same_csr_outstanding":{"max_time":3.0,"sim_time":1525.1658149999998,"passed":1,"total":1,"percent":100.0}},"passed":4,"total":4,"percent":100.0}},"passed":7,"total":7,"percent":100.0},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"rram_ctrl_tl_intg_err":{"max_time":2.0,"sim_time":888.618521,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"unmapped":{"testpoints":{"Unmapped":{"tests":{"rram_ctrl_stress_all_with_rand_reset":{"max_time":2.0,"sim_time":1459.744533,"passed":0,"total":1,"percent":0.0},"rram_ctrl_stress_all":{"max_time":4.0,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":2,"percent":0.0}},"passed":0,"total":2,"percent":0.0}},"coverage":{"code":{"block":87.06,"line_statement":88.8,"branch":71.91,"condition_expression":null,"toggle":38.19,"fsm":16.67},"assertion":79.77,"functional":45.34},"cov_report_page":"/nightly/current_run/scratch/master/rram_ctrl-sim-xcelium/cov_report/index.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"UVM_WARNING [BDTYP] Cannot create an object of type 'rram_ctrl_stress_all_vseq' because it is not registered with the factory.":[{"name":"rram_ctrl_stress_all_with_rand_reset","qual_name":"0.rram_ctrl_stress_all_with_rand_reset.103437809344072187115550560163448783110300459515197903755209203346608306701329","seed":103437809344072187115550560163448783110300459515197903755209203346608306701329,"line":86,"log_path":"/nightly/current_run/scratch/master/rram_ctrl-sim-xcelium/0.rram_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 1459744533 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT] \n","#### Factory Configuration (*)\n","\n","Instance Overrides:\n"]},{"name":"rram_ctrl_stress_all","qual_name":"0.rram_ctrl_stress_all.60339730423010809380219847718724401581001811383878838844381596692674982696822","seed":60339730423010809380219847718724401581001811383878838844381596692674982696822,"line":85,"log_path":"/nightly/current_run/scratch/master/rram_ctrl-sim-xcelium/0.rram_ctrl_stress_all/latest/run.log","log_context":["UVM_INFO @         0 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT] \n","#### Factory Configuration (*)\n","\n","Instance Overrides:\n"]}],"UVM_FATAL (cip_base_vseq__tl_errors.svh:476) [rram_ctrl_common_vseq] Check failed (cfg.tl_intg_alert_name inside {cfg.list_of_alerts}) tl intg alert (fatal_fault) is not inside '{\"recov_err\", \"fatal_std_err\", \"fatal_err\", \"fatal_macro_err\", \"recov_macro_err\"}":[{"name":"rram_ctrl_tl_intg_err","qual_name":"0.rram_ctrl_tl_intg_err.71092321995763178387073991579748518338124754926644645586586548399820409455125","seed":71092321995763178387073991579748518338124754926644645586586548399820409455125,"line":94,"log_path":"/nightly/current_run/scratch/master/rram_ctrl-sim-xcelium/0.rram_ctrl_tl_intg_err/latest/run.log","log_context":["UVM_INFO @ 888618521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":12,"total":15,"percent":80.0}