2144e83| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | adc_ctrl_smoke | 32.000s | 6.147ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | adc_ctrl_csr_hw_reset | 5.000s | 837.259us | 5 | 5 | 100.00 |
| V1 | csr_rw | adc_ctrl_csr_rw | 5.000s | 404.988us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | adc_ctrl_csr_bit_bash | 31.000s | 18.540ms | 0 | 5 | 0.00 |
| V1 | csr_aliasing | adc_ctrl_csr_aliasing | 9.000s | 1.262ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | adc_ctrl_csr_mem_rw_with_rand_reset | 6.000s | 557.307us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | adc_ctrl_csr_rw | 5.000s | 404.988us | 20 | 20 | 100.00 |
| adc_ctrl_csr_aliasing | 9.000s | 1.262ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 100 | 105 | 95.24 | |||
| V2 | filters_polled | adc_ctrl_filters_polled | 32.317m | 499.311ms | 50 | 50 | 100.00 |
| V2 | filters_polled_fixed | adc_ctrl_filters_polled_fixed | 31.117m | 498.881ms | 50 | 50 | 100.00 |
| V2 | filters_interrupt | adc_ctrl_filters_interrupt | 28.433m | 481.783ms | 49 | 50 | 98.00 |
| V2 | filters_interrupt_fixed | adc_ctrl_filters_interrupt_fixed | 33.483m | 486.761ms | 50 | 50 | 100.00 |
| V2 | filters_wakeup | adc_ctrl_filters_wakeup | 36.950m | 639.530ms | 50 | 50 | 100.00 |
| V2 | filters_wakeup_fixed | adc_ctrl_filters_wakeup_fixed | 34.600m | 591.845ms | 50 | 50 | 100.00 |
| V2 | filters_both | adc_ctrl_filters_both | 30.317m | 526.570ms | 49 | 50 | 98.00 |
| V2 | clock_gating | adc_ctrl_clock_gating | 30.683m | 623.386ms | 36 | 50 | 72.00 |
| V2 | poweron_counter | adc_ctrl_poweron_counter | 25.000s | 5.347ms | 50 | 50 | 100.00 |
| V2 | lowpower_counter | adc_ctrl_lowpower_counter | 3.433m | 43.777ms | 50 | 50 | 100.00 |
| V2 | fsm_reset | adc_ctrl_fsm_reset | 6.000s | 517.867us | 0 | 50 | 0.00 |
| V2 | stress_all | adc_ctrl_stress_all | 42.533m | 10.000s | 28 | 50 | 56.00 |
| V2 | alert_test | adc_ctrl_alert_test | 5.000s | 477.443us | 50 | 50 | 100.00 |
| V2 | intr_test | adc_ctrl_intr_test | 6.000s | 515.881us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | adc_ctrl_tl_errors | 6.000s | 524.304us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | adc_ctrl_tl_errors | 6.000s | 524.304us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | adc_ctrl_csr_hw_reset | 5.000s | 837.259us | 5 | 5 | 100.00 |
| adc_ctrl_csr_rw | 5.000s | 404.988us | 20 | 20 | 100.00 | ||
| adc_ctrl_csr_aliasing | 9.000s | 1.262ms | 5 | 5 | 100.00 | ||
| adc_ctrl_same_csr_outstanding | 22.000s | 4.731ms | 19 | 20 | 95.00 | ||
| V2 | tl_d_partial_access | adc_ctrl_csr_hw_reset | 5.000s | 837.259us | 5 | 5 | 100.00 |
| adc_ctrl_csr_rw | 5.000s | 404.988us | 20 | 20 | 100.00 | ||
| adc_ctrl_csr_aliasing | 9.000s | 1.262ms | 5 | 5 | 100.00 | ||
| adc_ctrl_same_csr_outstanding | 22.000s | 4.731ms | 19 | 20 | 95.00 | ||
| V2 | TOTAL | 651 | 740 | 87.97 | |||
| V2S | tl_intg_err | adc_ctrl_sec_cm | 37.000s | 7.807ms | 5 | 5 | 100.00 |
| adc_ctrl_tl_intg_err | 37.000s | 7.841ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | adc_ctrl_tl_intg_err | 37.000s | 7.841ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | adc_ctrl_stress_all_with_rand_reset | 30.000s | 14.354ms | 31 | 50 | 62.00 |
| V3 | TOTAL | 31 | 50 | 62.00 | |||
| TOTAL | 807 | 920 | 87.72 |
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/adc_ctrl-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_adc_ctrl_*/rtl/adc_ctrl_fsm.sv,385): Assertion NpCntClrPwrDn_A has failed has 88 failures:
0.adc_ctrl_fsm_reset.37102222209275537190153093195983946464265853572474066515050817224137228408652
Line 166, in log /nightly/current_run/scratch/master/adc_ctrl-sim-xcelium/0.adc_ctrl_fsm_reset/latest/run.log
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/adc_ctrl-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_fsm.sv,385): (time 419502954 PS) Assertion tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.NpCntClrPwrDn_A has failed
UVM_ERROR @ 419502954 ps: (adc_ctrl_fsm.sv:385) [ASSERT FAILED] NpCntClrPwrDn_A
UVM_INFO @ 419502954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.adc_ctrl_fsm_reset.91221444733289296487603795294811883834491037105759849924774676022486759144317
Line 166, in log /nightly/current_run/scratch/master/adc_ctrl-sim-xcelium/1.adc_ctrl_fsm_reset/latest/run.log
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/adc_ctrl-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_fsm.sv,385): (time 484391967 PS) Assertion tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.NpCntClrPwrDn_A has failed
UVM_ERROR @ 484391967 ps: (adc_ctrl_fsm.sv:385) [ASSERT FAILED] NpCntClrPwrDn_A
UVM_INFO @ 484391967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 48 more failures.
1.adc_ctrl_stress_all.83547306854828495454298111498562650838748697144257468084054721993209042107452
Line 179, in log /nightly/current_run/scratch/master/adc_ctrl-sim-xcelium/1.adc_ctrl_stress_all/latest/run.log
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/adc_ctrl-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_fsm.sv,385): (time 7984304132 PS) Assertion tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.NpCntClrPwrDn_A has failed
UVM_ERROR @ 7984304132 ps: (adc_ctrl_fsm.sv:385) [ASSERT FAILED] NpCntClrPwrDn_A
UVM_INFO @ 7984304132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.adc_ctrl_stress_all.85750442433012109826530988594620285358332824448733238253696600199520002727777
Line 169, in log /nightly/current_run/scratch/master/adc_ctrl-sim-xcelium/2.adc_ctrl_stress_all/latest/run.log
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/adc_ctrl-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_fsm.sv,385): (time 6280440536 PS) Assertion tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.NpCntClrPwrDn_A has failed
UVM_ERROR @ 6280440536 ps: (adc_ctrl_fsm.sv:385) [ASSERT FAILED] NpCntClrPwrDn_A
UVM_INFO @ 6280440536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 18 more failures.
7.adc_ctrl_stress_all_with_rand_reset.27717135469363513608797631116035436657130111149903469564660784083772211864693
Line 197, in log /nightly/current_run/scratch/master/adc_ctrl-sim-xcelium/7.adc_ctrl_stress_all_with_rand_reset/latest/run.log
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/adc_ctrl-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_fsm.sv,385): (time 1267950596 PS) Assertion tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.NpCntClrPwrDn_A has failed
UVM_ERROR @ 1267950596 ps: (adc_ctrl_fsm.sv:385) [ASSERT FAILED] NpCntClrPwrDn_A
UVM_INFO @ 1267950596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.adc_ctrl_stress_all_with_rand_reset.114185632775322199240490417080123696595025839968854837932031369809591720251810
Line 280, in log /nightly/current_run/scratch/master/adc_ctrl-sim-xcelium/11.adc_ctrl_stress_all_with_rand_reset/latest/run.log
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/adc_ctrl-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_fsm.sv,385): (time 62638159048 PS) Assertion tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.NpCntClrPwrDn_A has failed
UVM_ERROR @ 62638159048 ps: (adc_ctrl_fsm.sv:385) [ASSERT FAILED] NpCntClrPwrDn_A
UVM_INFO @ 62638159048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 16 more failures.
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 13 failures:
Test adc_ctrl_clock_gating has 10 failures.
5.adc_ctrl_clock_gating.78569738204453336131337919789787454894380074755924498423259014766005935016303
Line 162, in log /nightly/current_run/scratch/master/adc_ctrl-sim-xcelium/5.adc_ctrl_clock_gating/latest/run.log
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.adc_ctrl_clock_gating.57507990007357573303096681550133193016778383415451735453585258025691717101165
Line 155, in log /nightly/current_run/scratch/master/adc_ctrl-sim-xcelium/11.adc_ctrl_clock_gating/latest/run.log
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
Test adc_ctrl_stress_all has 2 failures.
14.adc_ctrl_stress_all.36746467159452117410250109245744214645753192582037293688955558134429624159782
Line 156, in log /nightly/current_run/scratch/master/adc_ctrl-sim-xcelium/14.adc_ctrl_stress_all/latest/run.log
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
16.adc_ctrl_stress_all.75626876010393701804320695439113632081017644877049174111336551899090362259485
Line 165, in log /nightly/current_run/scratch/master/adc_ctrl-sim-xcelium/16.adc_ctrl_stress_all/latest/run.log
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test adc_ctrl_filters_both has 1 failures.
33.adc_ctrl_filters_both.29017126588912602141666278402364583529897590875484437023259900979836741094747
Line 167, in log /nightly/current_run/scratch/master/adc_ctrl-sim-xcelium/33.adc_ctrl_filters_both/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/adc_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_ip_adc_ctrl_*/rtl/adc_ctrl_fsm.sv,382): Assertion LpSampleCntCfg_M has failed has 6 failures:
0.adc_ctrl_csr_bit_bash.68102101837235454287355004842035532948324546016932933483296434791446581942977
Line 163, in log /nightly/current_run/scratch/master/adc_ctrl-sim-xcelium/0.adc_ctrl_csr_bit_bash/latest/run.log
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/adc_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_fsm.sv,382): (time 19452743494 PS) Assertion tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.LpSampleCntCfg_M has failed
UVM_ERROR @ 19452743494 ps: (adc_ctrl_fsm.sv:382) [ASSERT FAILED] LpSampleCntCfg_M
UVM_INFO @ 19452743494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.adc_ctrl_csr_bit_bash.44788583037323666700989222690348265144610657449903053546369389460406552081284
Line 163, in log /nightly/current_run/scratch/master/adc_ctrl-sim-xcelium/1.adc_ctrl_csr_bit_bash/latest/run.log
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/adc_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_fsm.sv,382): (time 2719717635 PS) Assertion tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.LpSampleCntCfg_M has failed
UVM_ERROR @ 2719717635 ps: (adc_ctrl_fsm.sv:382) [ASSERT FAILED] LpSampleCntCfg_M
UVM_INFO @ 2719717635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
2.adc_ctrl_same_csr_outstanding.74545939745387384903538934336117842178210632875230412528038691467184708000723
Line 164, in log /nightly/current_run/scratch/master/adc_ctrl-sim-xcelium/2.adc_ctrl_same_csr_outstanding/latest/run.log
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/adc_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_fsm.sv,382): (time 4405670418 PS) Assertion tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.LpSampleCntCfg_M has failed
UVM_ERROR @ 4405670418 ps: (adc_ctrl_fsm.sv:382) [ASSERT FAILED] LpSampleCntCfg_M
UVM_INFO @ 4405670418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 5 failures:
1.adc_ctrl_clock_gating.106862257601947962637866575533572552586236080115895241609028415063368130364204
Line 169, in log /nightly/current_run/scratch/master/adc_ctrl-sim-xcelium/1.adc_ctrl_clock_gating/latest/run.log
UVM_ERROR @ 375888114496 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 375888114496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.adc_ctrl_clock_gating.16991827998393958147570868920270392714878307769532895159744005256798343668394
Line 155, in log /nightly/current_run/scratch/master/adc_ctrl-sim-xcelium/9.adc_ctrl_clock_gating/latest/run.log
UVM_ERROR @ 4530962537 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 4530962537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
20.adc_ctrl_stress_all_with_rand_reset.47618940997416221187323410291648246651500916034374103063834693783902211325022
Line 204, in log /nightly/current_run/scratch/master/adc_ctrl-sim-xcelium/20.adc_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 35634898092 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 35634898092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (adc_ctrl_scoreboard.sv:406) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state has 1 failures:
10.adc_ctrl_filters_interrupt.52721104805578363934422705283580053663626283107970695088162314268682000440742
Line 161, in log /nightly/current_run/scratch/master/adc_ctrl-sim-xcelium/10.adc_ctrl_filters_interrupt/latest/run.log
UVM_ERROR @ 326061269375 ps: (adc_ctrl_scoreboard.sv:406) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
UVM_INFO @ 326061269375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job returned non-zero exit code has 1 failures:
cov_merge
Log /nightly/current_run/scratch/master/adc_ctrl-sim-xcelium/cov_merge/merged/cov_merge.log
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk cov_merge cov_merge_cmd=imc cov_merge_opts='-64bit -licqueue -exec /nightly/current_run/opentitan/hw/dv/tools/xcelium/cov_merge.tcl'
[make]: cov_merge
imc -64bit -licqueue -exec /nightly/current_run/opentitan/hw/dv/tools/xcelium/cov_merge.tcl
*I,imc.tool.cov.version.diff: "There is a difference between the IMC tool version 22.09 and the coverage version 21.09-s006"
Error: Cannot invoke "jdk.internal.platform.CgroupInfo.getMountPoint()" because "<parameter1>" is null
Created log file /nightly/current_run/opentitan/startup.log
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:231: cov_merge] Error 1
Job killed most likely because its dependent job failed. has 1 failures: