AES/MASKED Simulation Results

Tuesday September 09 2025 00:00:40 UTC

GitHub Revision: `2144e83`

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	67.903us	1	1	100.00
V1	smoke	aes_smoke	10.000s	307.012us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	85.787us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	243.878us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	8.000s	1.956ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	4.000s	224.775us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	3.000s	82.362us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	243.878us	20	20	100.00
		aes_csr_aliasing	4.000s	224.775us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	10.000s	307.012us	50	50	100.00
		aes_config_error	7.000s	1.613ms	50	50	100.00
		aes_stress	10.000s	949.085us	50	50	100.00
V2	key_length	aes_smoke	10.000s	307.012us	50	50	100.00
		aes_config_error	7.000s	1.613ms	50	50	100.00
		aes_stress	10.000s	949.085us	50	50	100.00
V2	back2back	aes_stress	10.000s	949.085us	50	50	100.00
		aes_b2b	33.000s	1.119ms	50	50	100.00
V2	backpressure	aes_stress	10.000s	949.085us	50	50	100.00
V2	multi_message	aes_smoke	10.000s	307.012us	50	50	100.00
		aes_config_error	7.000s	1.613ms	50	50	100.00
		aes_stress	10.000s	949.085us	50	50	100.00
		aes_alert_reset	16.000s	895.815us	50	50	100.00
V2	failure_test	aes_man_cfg_err	6.000s	109.498us	50	50	100.00
		aes_config_error	7.000s	1.613ms	50	50	100.00
		aes_alert_reset	16.000s	895.815us	50	50	100.00
V2	trigger_clear_test	aes_clear	14.000s	858.363us	49	50	98.00
V2	nist_test_vectors	aes_nist_vectors	23.000s	1.167ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	16.000s	895.815us	50	50	100.00
V2	stress	aes_stress	10.000s	949.085us	50	50	100.00
V2	sideload	aes_stress	10.000s	949.085us	50	50	100.00
		aes_sideload	10.000s	849.336us	50	50	100.00
V2	deinitialization	aes_deinit	12.000s	543.239us	50	50	100.00
V2	stress_all	aes_stress_all	1.150m	1.342ms	10	10	100.00
V2	alert_test	aes_alert_test	5.000s	53.532us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	5.000s	92.051us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	5.000s	92.051us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	85.787us	5	5	100.00
		aes_csr_rw	3.000s	243.878us	20	20	100.00
		aes_csr_aliasing	4.000s	224.775us	5	5	100.00
		aes_same_csr_outstanding	4.000s	142.694us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	85.787us	5	5	100.00
		aes_csr_rw	3.000s	243.878us	20	20	100.00
		aes_csr_aliasing	4.000s	224.775us	5	5	100.00
		aes_same_csr_outstanding	4.000s	142.694us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	55.000s	2.624ms	50	50	100.00
V2S	fault_inject	aes_fi	42.000s	2.967ms	50	50	100.00
		aes_control_fi	29.000s	10.100ms	283	300	94.33
		aes_cipher_fi	29.000s	10.007ms	337	350	96.29
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	217.642us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	217.642us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	217.642us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	217.642us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	5.000s	1.575ms	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	11.000s	646.405us	5	5	100.00
		aes_tl_intg_err	5.000s	801.532us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	801.532us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	16.000s	895.815us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	217.642us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	10.000s	307.012us	50	50	100.00
		aes_stress	10.000s	949.085us	50	50	100.00
		aes_alert_reset	16.000s	895.815us	50	50	100.00
		aes_core_fi	9.000s	1.102ms	70	70	100.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	217.642us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	6.000s	214.435us	50	50	100.00
		aes_stress	10.000s	949.085us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	10.000s	949.085us	50	50	100.00
		aes_sideload	10.000s	849.336us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	6.000s	214.435us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	6.000s	214.435us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	6.000s	214.435us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	6.000s	214.435us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	6.000s	214.435us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	10.000s	949.085us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	10.000s	949.085us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	42.000s	2.967ms	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	42.000s	2.967ms	50	50	100.00
		aes_control_fi	29.000s	10.100ms	283	300	94.33
		aes_cipher_fi	29.000s	10.007ms	337	350	96.29
		aes_ctr_fi	5.000s	282.953us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	42.000s	2.967ms	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	42.000s	2.967ms	50	50	100.00
		aes_control_fi	29.000s	10.100ms	283	300	94.33
		aes_cipher_fi	29.000s	10.007ms	337	350	96.29
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	29.000s	10.007ms	337	350	96.29
V2S	sec_cm_ctr_fsm_sparse	aes_fi	42.000s	2.967ms	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	42.000s	2.967ms	50	50	100.00
		aes_control_fi	29.000s	10.100ms	283	300	94.33
		aes_ctr_fi	5.000s	282.953us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	42.000s	2.967ms	50	50	100.00
		aes_control_fi	29.000s	10.100ms	283	300	94.33
		aes_cipher_fi	29.000s	10.007ms	337	350	96.29
		aes_ctr_fi	5.000s	282.953us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	16.000s	895.815us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	42.000s	2.967ms	50	50	100.00
		aes_control_fi	29.000s	10.100ms	283	300	94.33
		aes_cipher_fi	29.000s	10.007ms	337	350	96.29
		aes_ctr_fi	5.000s	282.953us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	42.000s	2.967ms	50	50	100.00
		aes_control_fi	29.000s	10.100ms	283	300	94.33
		aes_cipher_fi	29.000s	10.007ms	337	350	96.29
		aes_ctr_fi	5.000s	282.953us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	42.000s	2.967ms	50	50	100.00
		aes_control_fi	29.000s	10.100ms	283	300	94.33
		aes_ctr_fi	5.000s	282.953us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	42.000s	2.967ms	50	50	100.00
		aes_control_fi	29.000s	10.100ms	283	300	94.33
		aes_cipher_fi	29.000s	10.007ms	337	350	96.29
V2S		TOTAL			955	985	96.95
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	27.000s	6.362ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1561	1602	97.44

Failure Buckets

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 11 failures:
- Test aes_cipher_fi has 11 failures.
  - 6.aes_cipher_fi.43610181243806385042017352419979777242234046762826410063644053533837695696757
    Line 144, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/6.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10041726046 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10041726046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 20.aes_cipher_fi.39018085000328881132394680576631224764913115626891732410645092147355606636013
    Line 137, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/20.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10009344176 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009344176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 9 more failures.
Job timed out after * minutes has 11 failures:
- Test aes_control_fi has 9 failures.
  - 7.aes_control_fi.95893187831424618986362010885745826988398999231214155785885175107788553123739
    Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/7.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 25.aes_control_fi.106471022830832070422173546644358518843387858252867276256285001398386207412252
    Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/25.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 7 more failures.
- Test aes_cipher_fi has 2 failures.
  - 41.aes_cipher_fi.106970906202892616065097910049630812556925403075121148212699725883133118764180
    Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/41.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 296.aes_cipher_fi.22850089472819237511097134848568110917536949601996199111630482959179835535376
    Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/296.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_control_fi has 8 failures.
  - 129.aes_control_fi.1915477991651911702866233282232999818268353694428358386620591740142743357757
    Line 137, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/129.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10012505622 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012505622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 173.aes_control_fi.108954117356805917218284075553892163453223061385417160615542875509824796225416
    Line 145, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/173.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10006692216 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006692216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 6 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

1.aes_stress_all_with_rand_reset.41394098732999212516831165678256626205608860294215159803765254845414332795358
Line 482, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2161592724 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2161592724 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.85633567938505732752175277752080514966240757073842248185298482756554139572666
Line 250, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 404960633 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 404960633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 4.aes_stress_all_with_rand_reset.16343289617927877833791354575675510115210419550744228713657824236651585282078
    Line 809, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1371874606 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 1371874606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 6.aes_stress_all_with_rand_reset.75515650615306236922010557775469010807810892887377310066968691909011985596631
    Line 138, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 147588239 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 147588239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:946) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 0.aes_stress_all_with_rand_reset.5995973869055617877142163350008511596427623259929405259878266859273792991555
    Line 129, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 226618138 ps: (cip_base_vseq.sv:946) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 226618138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 9.aes_stress_all_with_rand_reset.2804754314651171718597898556205904817040582043093622249880934521427818575914
    Line 179, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 238985091 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 238985091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_scoreboard.sv:611) scoreboard [scoreboard] # * has 1 failures:
- Test aes_clear has 1 failures.
  - 16.aes_clear.32019970505191596752521151883598172356222382234900108847288591886542034249666
    Line 11963, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/16.aes_clear/latest/run.log
```
  UVM_FATAL @  32993120 ps: (aes_scoreboard.sv:611) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]  # 1
           TEST FAILED MESSAGES DID NOT MATCH

                 0 37 	 71 	 7f 	 0
                 1 16 	 53 	 7e 	 0
```

Job returned non-zero exit code has 1 failures:

Test aes has 1 failures.

cov_merge
Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/cov_merge/merged/cov_merge.log

  [Executing]:
  make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk cov_merge cov_merge_cmd=imc cov_merge_opts='-64bit -licqueue -exec /nightly/current_run/opentitan/hw/dv/tools/xcelium/cov_merge.tcl'

  [make]: cov_merge
  imc -64bit -licqueue -exec /nightly/current_run/opentitan/hw/dv/tools/xcelium/cov_merge.tcl
  *I,imc.tool.cov.version.diff: "There is a difference between the IMC tool version 22.09 and the coverage version 21.09-s006"
  Error: Cannot invoke "jdk.internal.platform.CgroupInfo.getMountPoint()" because "<parameter1>" is null
  Created log file /nightly/current_run/opentitan/startup.log
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:231: cov_merge] Error 1

Job killed most likely because its dependent job failed. has 1 failures:
- Test aes has 1 failures.
  - cov_report
    Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/cov_report/cov_report.log