AES/UNMASKED Simulation Results

Tuesday September 09 2025 00:00:40 UTC

GitHub Revision: `2144e83`

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	8.000s	166.060us	1	1	100.00
V1	smoke	aes_smoke	8.000s	103.245us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	66.202us	5	5	100.00
V1	csr_rw	aes_csr_rw	7.000s	82.649us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	10.979ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	106.070us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	95.433us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	7.000s	82.649us	20	20	100.00
		aes_csr_aliasing	5.000s	106.070us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	8.000s	103.245us	50	50	100.00
		aes_config_error	9.000s	92.203us	50	50	100.00
		aes_stress	9.000s	199.660us	50	50	100.00
V2	key_length	aes_smoke	8.000s	103.245us	50	50	100.00
		aes_config_error	9.000s	92.203us	50	50	100.00
		aes_stress	9.000s	199.660us	50	50	100.00
V2	back2back	aes_stress	9.000s	199.660us	50	50	100.00
		aes_b2b	10.000s	95.663us	50	50	100.00
V2	backpressure	aes_stress	9.000s	199.660us	50	50	100.00
V2	multi_message	aes_smoke	8.000s	103.245us	50	50	100.00
		aes_config_error	9.000s	92.203us	50	50	100.00
		aes_stress	9.000s	199.660us	50	50	100.00
		aes_alert_reset	9.000s	78.120us	50	50	100.00
V2	failure_test	aes_man_cfg_err	8.000s	61.439us	50	50	100.00
		aes_config_error	9.000s	92.203us	50	50	100.00
		aes_alert_reset	9.000s	78.120us	50	50	100.00
V2	trigger_clear_test	aes_clear	9.000s	462.092us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	10.000s	234.908us	1	1	100.00
V2	reset_recovery	aes_alert_reset	9.000s	78.120us	50	50	100.00
V2	stress	aes_stress	9.000s	199.660us	50	50	100.00
V2	sideload	aes_stress	9.000s	199.660us	50	50	100.00
		aes_sideload	9.000s	201.147us	50	50	100.00
V2	deinitialization	aes_deinit	9.000s	91.455us	50	50	100.00
V2	stress_all	aes_stress_all	22.000s	629.922us	10	10	100.00
V2	alert_test	aes_alert_test	8.000s	175.560us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	5.000s	132.251us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	5.000s	132.251us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	66.202us	5	5	100.00
		aes_csr_rw	7.000s	82.649us	20	20	100.00
		aes_csr_aliasing	5.000s	106.070us	5	5	100.00
		aes_same_csr_outstanding	4.000s	112.612us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	66.202us	5	5	100.00
		aes_csr_rw	7.000s	82.649us	20	20	100.00
		aes_csr_aliasing	5.000s	106.070us	5	5	100.00
		aes_same_csr_outstanding	4.000s	112.612us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	10.000s	1.341ms	50	50	100.00
V2S	fault_inject	aes_fi	9.000s	75.081us	50	50	100.00
		aes_control_fi	41.000s	10.015ms	275	300	91.67
		aes_cipher_fi	48.000s	10.003ms	320	350	91.43
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	154.401us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	154.401us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	154.401us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	154.401us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	245.266us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	10.000s	1.081ms	5	5	100.00
		aes_tl_intg_err	5.000s	197.824us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	197.824us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	9.000s	78.120us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	154.401us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	8.000s	103.245us	50	50	100.00
		aes_stress	9.000s	199.660us	50	50	100.00
		aes_alert_reset	9.000s	78.120us	50	50	100.00
		aes_core_fi	27.000s	10.018ms	65	70	92.86
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	154.401us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	8.000s	56.097us	50	50	100.00
		aes_stress	9.000s	199.660us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	9.000s	199.660us	50	50	100.00
		aes_sideload	9.000s	201.147us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	8.000s	56.097us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	8.000s	56.097us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	8.000s	56.097us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	8.000s	56.097us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	8.000s	56.097us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	9.000s	199.660us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	9.000s	199.660us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	9.000s	75.081us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	9.000s	75.081us	50	50	100.00
		aes_control_fi	41.000s	10.015ms	275	300	91.67
		aes_cipher_fi	48.000s	10.003ms	320	350	91.43
		aes_ctr_fi	8.000s	156.995us	49	50	98.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	9.000s	75.081us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	9.000s	75.081us	50	50	100.00
		aes_control_fi	41.000s	10.015ms	275	300	91.67
		aes_cipher_fi	48.000s	10.003ms	320	350	91.43
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	48.000s	10.003ms	320	350	91.43
V2S	sec_cm_ctr_fsm_sparse	aes_fi	9.000s	75.081us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	9.000s	75.081us	50	50	100.00
		aes_control_fi	41.000s	10.015ms	275	300	91.67
		aes_ctr_fi	8.000s	156.995us	49	50	98.00
V2S	sec_cm_ctrl_sparse	aes_fi	9.000s	75.081us	50	50	100.00
		aes_control_fi	41.000s	10.015ms	275	300	91.67
		aes_cipher_fi	48.000s	10.003ms	320	350	91.43
		aes_ctr_fi	8.000s	156.995us	49	50	98.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	9.000s	78.120us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	9.000s	75.081us	50	50	100.00
		aes_control_fi	41.000s	10.015ms	275	300	91.67
		aes_cipher_fi	48.000s	10.003ms	320	350	91.43
		aes_ctr_fi	8.000s	156.995us	49	50	98.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	9.000s	75.081us	50	50	100.00
		aes_control_fi	41.000s	10.015ms	275	300	91.67
		aes_cipher_fi	48.000s	10.003ms	320	350	91.43
		aes_ctr_fi	8.000s	156.995us	49	50	98.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	9.000s	75.081us	50	50	100.00
		aes_control_fi	41.000s	10.015ms	275	300	91.67
		aes_ctr_fi	8.000s	156.995us	49	50	98.00
V2S	sec_cm_data_reg_local_esc	aes_fi	9.000s	75.081us	50	50	100.00
		aes_control_fi	41.000s	10.015ms	275	300	91.67
		aes_cipher_fi	48.000s	10.003ms	320	350	91.43
V2S		TOTAL			924	985	93.81
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	15.000s	577.353us	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1531	1602	95.57

Failure Buckets

Job timed out after * minutes has 33 failures:
- Test aes_control_fi has 16 failures.
  - 16.aes_control_fi.77579166795284619216835674999676196168983822021280938073080758066171310656270
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/16.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 50.aes_control_fi.107230499247980900096677483439492192602073120758724638032862487682255806657795
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/50.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 14 more failures.
- Test aes_cipher_fi has 16 failures.
  - 19.aes_cipher_fi.104249914244793307210237443738298302927756106524487815799744936072339819791941
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/19.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 58.aes_cipher_fi.108680762529923885590480904573373575029192274390265225426890056970969697075264
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/58.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 14 more failures.
- Test aes_ctr_fi has 1 failures.
  - 36.aes_ctr_fi.49331355580761407905273394542201686800766871403756484650596372444691039915437
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/36.aes_ctr_fi/latest/run.log
```
  Job timed out after 1 minutes
```
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 14 failures:
- Test aes_cipher_fi has 14 failures.
  - 2.aes_cipher_fi.7375927074304092174263785329289399675872219393660337936931135256766588104292
    Line 138, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/2.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10003171561 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003171561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 11.aes_cipher_fi.13901429830054899247359488739965195001313589427922039462008852768257617054430
    Line 134, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/11.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10020928879 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10020928879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 12 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_control_fi has 9 failures.
  - 28.aes_control_fi.34365153669300081102163417679351544021255260745181745475975609498682758771629
    Line 133, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/28.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10013906158 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013906158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 30.aes_control_fi.90829108085658745321414353830491290972838174756408233028361223018077011648386
    Line 136, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/30.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10004509317 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004509317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 7 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

1.aes_stress_all_with_rand_reset.4396802765196604867313866443282312382099718878844728854109118510188581075537
Line 929, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 577352732 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 577352732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.18737759009987821376951931792940400330178486083934813938895306012015499702477
Line 851, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 355159687 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 355159687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_core_fi has 5 failures.
  - 6.aes_core_fi.114328034776410907718897373049245182604984100425607357997031656940706556932365
    Line 141, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/6.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10004432466 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004432466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 23.aes_core_fi.110292151990690172520536078722984417359481414290503328097995707329278803569551
    Line 144, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/23.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10017607526 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10017607526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.
UVM_ERROR (cip_base_vseq.sv:946) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 0.aes_stress_all_with_rand_reset.36979078499753516362498949883491318072693048735114208013127057604585081428944
    Line 147, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 497573227 ps: (cip_base_vseq.sv:946) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 497573227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 4.aes_stress_all_with_rand_reset.2772677582803802255924234009950638121037814074930756054115342680639426927698
    Line 165, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  46591799 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  46591799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 5.aes_stress_all_with_rand_reset.84034410651578851048774027856417549341758433817475799773442840454008881794876
    Line 145, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  18407375 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  18407375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 6.aes_stress_all_with_rand_reset.73759821407671992769812313713611463307568914780125036933600467812685197422569
    Line 298, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 134712055 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 134712055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 1 failures:

Test aes has 1 failures.

cov_merge
Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/cov_merge/merged/cov_merge.log

  [Executing]:
  make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk cov_merge cov_merge_cmd=imc cov_merge_opts='-64bit -licqueue -exec /nightly/current_run/opentitan/hw/dv/tools/xcelium/cov_merge.tcl'

  [make]: cov_merge
  imc -64bit -licqueue -exec /nightly/current_run/opentitan/hw/dv/tools/xcelium/cov_merge.tcl
  *I,imc.tool.cov.version.diff: "There is a difference between the IMC tool version 22.09 and the coverage version 21.09-s006"
  Error: Cannot invoke "jdk.internal.platform.CgroupInfo.getMountPoint()" because "<parameter1>" is null
  Created log file /nightly/current_run/opentitan/startup.log
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:231: cov_merge] Error 1

Job killed most likely because its dependent job failed. has 1 failures:
- Test aes has 1 failures.
  - cov_report
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/cov_report/cov_report.log