CSRNG Simulation Results

Tuesday September 09 2025 00:00:40 UTC

GitHub Revision: 2144e83

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	9.000s	347.121us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	17.826us	5	5	100.00
V1	csr_rw	csrng_csr_rw	4.000s	16.412us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	29.000s	1.391ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	8.000s	140.521us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	5.000s	53.143us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	4.000s	16.412us	20	20	100.00
		csrng_csr_aliasing	8.000s	140.521us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	26.000s	1.263ms	181	200	90.50
V2	alerts	csrng_alert	1.033m	3.408ms	500	500	100.00
V2	err	csrng_err	9.000s	38.846us	465	500	93.00
V2	cmds	csrng_cmds	13.983m	58.616ms	50	50	100.00
V2	life cycle	csrng_cmds	13.983m	58.616ms	50	50	100.00
V2	stress_all	csrng_stress_all	24.950m	91.376ms	47	50	94.00
V2	intr_test	csrng_intr_test	4.000s	25.254us	50	50	100.00
V2	alert_test	csrng_alert_test	6.000s	169.406us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	16.000s	887.058us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	16.000s	887.058us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	17.826us	5	5	100.00
		csrng_csr_rw	4.000s	16.412us	20	20	100.00
		csrng_csr_aliasing	8.000s	140.521us	5	5	100.00
		csrng_same_csr_outstanding	8.000s	216.779us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	17.826us	5	5	100.00
		csrng_csr_rw	4.000s	16.412us	20	20	100.00
		csrng_csr_aliasing	8.000s	140.521us	5	5	100.00
		csrng_same_csr_outstanding	8.000s	216.779us	20	20	100.00
V2		TOTAL			1383	1440	96.04
V2S	tl_intg_err	csrng_sec_cm	12.000s	531.400us	5	5	100.00
		csrng_tl_intg_err	15.000s	310.474us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	5.000s	22.412us	50	50	100.00
		csrng_csr_rw	4.000s	16.412us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.033m	3.408ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	24.950m	91.376ms	47	50	94.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	26.000s	1.263ms	181	200	90.50
		csrng_err	9.000s	38.846us	465	500	93.00
		csrng_sec_cm	12.000s	531.400us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	26.000s	1.263ms	181	200	90.50
		csrng_err	9.000s	38.846us	465	500	93.00
		csrng_sec_cm	12.000s	531.400us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	26.000s	1.263ms	181	200	90.50
		csrng_err	9.000s	38.846us	465	500	93.00
		csrng_sec_cm	12.000s	531.400us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	26.000s	1.263ms	181	200	90.50
		csrng_err	9.000s	38.846us	465	500	93.00
		csrng_sec_cm	12.000s	531.400us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	26.000s	1.263ms	181	200	90.50
		csrng_err	9.000s	38.846us	465	500	93.00
		csrng_sec_cm	12.000s	531.400us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	26.000s	1.263ms	181	200	90.50
		csrng_err	9.000s	38.846us	465	500	93.00
		csrng_sec_cm	12.000s	531.400us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	26.000s	1.263ms	181	200	90.50
		csrng_err	9.000s	38.846us	465	500	93.00
		csrng_sec_cm	12.000s	531.400us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.033m	3.408ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	26.000s	1.263ms	181	200	90.50
		csrng_err	9.000s	38.846us	465	500	93.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	24.950m	91.376ms	47	50	94.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.033m	3.408ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	15.000s	310.474us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	26.000s	1.263ms	181	200	90.50
		csrng_err	9.000s	38.846us	465	500	93.00
		csrng_sec_cm	12.000s	531.400us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	26.000s	1.263ms	181	200	90.50
		csrng_err	9.000s	38.846us	465	500	93.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	26.000s	1.263ms	181	200	90.50
		csrng_err	9.000s	38.846us	465	500	93.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	26.000s	1.263ms	181	200	90.50
		csrng_err	9.000s	38.846us	465	500	93.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	26.000s	1.263ms	181	200	90.50
		csrng_err	9.000s	38.846us	465	500	93.00
		csrng_sec_cm	12.000s	531.400us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	26.000s	1.263ms	181	200	90.50
		csrng_err	9.000s	38.846us	465	500	93.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	13.100m	41.593ms	10	10	100.00
V3		TOTAL			10	10	100.00
		TOTAL			1573	1630	96.50

Failure Buckets

• UVM_FATAL (csrng_base_vseq.sv:184) virtual_sequencer [csrng_err_vseq] has 22 failures:

  • Test csrng_err has 22 failures.

    • 37.csrng_err.112283188714300434962684511195003282695383233260619161654850991829278121606269
      Line 134, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/37.csrng_err/latest/run.log

        UVM_FATAL @   2887474 ps: (csrng_base_vseq.sv:184) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.csrng_err_vseq]
             ----| PATH NOT FOUND
        UVM_INFO @   2887474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 51.csrng_err.102899786835835551986290233060055289580971845418897923752370245491638944945669
      Line 134, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/51.csrng_err/latest/run.log

        UVM_FATAL @   2895941 ps: (csrng_base_vseq.sv:184) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.csrng_err_vseq]
             ----| PATH NOT FOUND
        UVM_INFO @   2895941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 20 more failures.

• UVM_FATAL (csrng_base_vseq.sv:189) virtual_sequencer [csrng_err_vseq] has 13 failures:

  • Test csrng_err has 13 failures.

    • 4.csrng_err.73448715478621599256783177506544245373275402272340730672390856311941407451327
      Line 134, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/4.csrng_err/latest/run.log

        UVM_FATAL @   2463388 ps: (csrng_base_vseq.sv:189) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.csrng_err_vseq]
             ----| PATH NOT FOUND
        UVM_INFO @   2463388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 34.csrng_err.45007268384587915971887040487361249422664861274390070751099757034878020384805
      Line 134, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/34.csrng_err/latest/run.log

        UVM_FATAL @  10094959 ps: (csrng_base_vseq.sv:189) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.csrng_err_vseq]
             ----| PATH NOT FOUND
        UVM_INFO @  10094959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 11 more failures.

• UVM_FATAL (csrng_base_vseq.sv:184) virtual_sequencer [csrng_intr_vseq] has 11 failures:

  • Test csrng_intr has 11 failures.

    • 7.csrng_intr.84224290120611315491046385710198635108557493425774110770434112788673107303447
      Line 134, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/7.csrng_intr/latest/run.log

        UVM_FATAL @  58752324 ps: (csrng_base_vseq.sv:184) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.csrng_intr_vseq]
             ----| PATH NOT FOUND
        UVM_INFO @  58752324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 23.csrng_intr.113040714531483627574137605420111476273922324840306647847969100633126386960881
      Line 134, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/23.csrng_intr/latest/run.log

        UVM_FATAL @ 296274240 ps: (csrng_base_vseq.sv:184) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.csrng_intr_vseq]
             ----| PATH NOT FOUND
        UVM_INFO @ 296274240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 9 more failures.

• UVM_FATAL (csrng_base_vseq.sv:189) virtual_sequencer [csrng_intr_vseq] has 8 failures:

  • Test csrng_intr has 8 failures.

    • 6.csrng_intr.81369158235512827968154023764975492922645926713378624331422206699810438849285
      Line 134, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/6.csrng_intr/latest/run.log

        UVM_FATAL @  46468139 ps: (csrng_base_vseq.sv:189) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.csrng_intr_vseq]
             ----| PATH NOT FOUND
        UVM_INFO @  46468139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 69.csrng_intr.62689483429205165676143797573868250233952323702556060886568241602992523272330
      Line 134, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/69.csrng_intr/latest/run.log

        UVM_FATAL @ 170067886 ps: (csrng_base_vseq.sv:189) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.csrng_intr_vseq]
             ----| PATH NOT FOUND
        UVM_INFO @ 170067886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 6 more failures.

• UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 3 failures:

  • Test csrng_stress_all has 3 failures.

    • 27.csrng_stress_all.69732249719928675330962427893265355519086169239762241494914182024767866524583
      Line 132, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/27.csrng_stress_all/latest/run.log

        UVM_ERROR @  54049301 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @  54049301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 28.csrng_stress_all.62725831074526355709914768660663540521549816064111902943599685168154757384085
      Line 132, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/28.csrng_stress_all/latest/run.log

        UVM_ERROR @ 155626696 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @ 155626696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• Job returned non-zero exit code has 1 failures:

  • Test csrng has 1 failures.

    • cov_merge
      Log /nightly/current_run/scratch/master/csrng-sim-xcelium/cov_merge/merged/cov_merge.log

        [Executing]:
        make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk cov_merge cov_merge_cmd=imc cov_merge_opts='-64bit -licqueue -exec /nightly/current_run/opentitan/hw/dv/tools/xcelium/cov_merge.tcl'
      
        [make]: cov_merge
        imc -64bit -licqueue -exec /nightly/current_run/opentitan/hw/dv/tools/xcelium/cov_merge.tcl
        *I,imc.tool.cov.version.diff: "There is a difference between the IMC tool version 22.09 and the coverage version 21.09-s006"
        Error: Cannot invoke "jdk.internal.platform.CgroupInfo.getMountPoint()" because "<parameter1>" is null
        Created log file /nightly/current_run/opentitan/startup.log
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:231: cov_merge] Error 1
      

• Job killed most likely because its dependent job failed. has 1 failures:

  • Test csrng has 1 failures.
    • cov_report
      Log /nightly/current_run/scratch/master/csrng-sim-xcelium/cov_report/cov_report.log