EDN Simulation Results

Tuesday September 09 2025 00:00:40 UTC

GitHub Revision: 2144e83

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	4.000s	34.292us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	3.000s	15.486us	5	5	100.00
V1	csr_rw	edn_csr_rw	3.000s	15.177us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	8.000s	175.600us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	5.000s	165.723us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	4.000s	45.532us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	3.000s	15.177us	20	20	100.00
		edn_csr_aliasing	5.000s	165.723us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	3.417m	19.804ms	300	300	100.00
V2	csrng_commands	edn_genbits	3.417m	19.804ms	300	300	100.00
V2	genbits	edn_genbits	3.417m	19.804ms	300	300	100.00
V2	interrupts	edn_intr	4.000s	22.697us	22	50	44.00
V2	alerts	edn_alert	4.000s	86.922us	200	200	100.00
V2	errs	edn_err	4.000s	6.827us	0	100	0.00
V2	disable	edn_disable	4.000s	28.982us	50	50	100.00
		edn_disable_auto_req_mode	4.000s	48.376us	50	50	100.00
V2	stress_all	edn_stress_all	11.000s	391.186us	50	50	100.00
V2	intr_test	edn_intr_test	3.000s	42.747us	50	50	100.00
V2	alert_test	edn_alert_test	4.000s	57.738us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	7.000s	149.771us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	7.000s	149.771us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	3.000s	15.486us	5	5	100.00
		edn_csr_rw	3.000s	15.177us	20	20	100.00
		edn_csr_aliasing	5.000s	165.723us	5	5	100.00
		edn_same_csr_outstanding	4.000s	26.980us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	3.000s	15.486us	5	5	100.00
		edn_csr_rw	3.000s	15.177us	20	20	100.00
		edn_csr_aliasing	5.000s	165.723us	5	5	100.00
		edn_same_csr_outstanding	4.000s	26.980us	20	20	100.00
V2		TOTAL			812	940	86.38
V2S	tl_intg_err	edn_sec_cm	11.000s	1.996ms	5	5	100.00
		edn_tl_intg_err	5.000s	180.491us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	3.000s	45.556us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	4.000s	86.922us	200	200	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	11.000s	1.996ms	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	11.000s	1.996ms	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	11.000s	1.996ms	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	11.000s	1.996ms	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	4.000s	86.922us	200	200	100.00
		edn_sec_cm	11.000s	1.996ms	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	4.000s	86.922us	200	200	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	5.000s	180.491us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	2.383m	10.848ms	30	50	60.00
V3		TOTAL			30	50	60.00
		TOTAL			982	1130	86.90

Failure Buckets

• xmsim: *E,ASRTST (/nightly/current_run/scratch/master/edn-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_count_*/rtl/prim_count.sv,300): Assertion CntErrReported_A has failed (* cycles, starting * PS) has 58 failures:

  • Test edn_err has 47 failures.

    • 0.edn_err.97836746366749115674987276346713186020258672038492295232926916273635603311218
      Line 144, in log /nightly/current_run/scratch/master/edn-sim-xcelium/0.edn_err/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/edn-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_count_0/rtl/prim_count.sv,300): (time 3626146 PS) Assertion tb.dut.u_edn_core.u_prim_count_max_reqs_cntr.CntErrReported_A has failed (2 cycles, starting 3605738 PS)
        UVM_ERROR @   3626146 ps: (prim_count.sv:300) [ASSERT FAILED] CntErrReported_A
        UVM_INFO @   3626146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.edn_err.92071368046905261587393711618268597310699097905026013584187052295874794787977
      Line 144, in log /nightly/current_run/scratch/master/edn-sim-xcelium/1.edn_err/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/edn-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_count_0/rtl/prim_count.sv,300): (time 6827445 PS) Assertion tb.dut.u_edn_core.u_prim_count_max_reqs_cntr.CntErrReported_A has failed (2 cycles, starting 6816692 PS)
        UVM_ERROR @   6827445 ps: (prim_count.sv:300) [ASSERT FAILED] CntErrReported_A
        UVM_INFO @   6827445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 45 more failures.

  • Test edn_intr has 11 failures.

    • 1.edn_intr.85196819656389556508380291247905343216651920508048357558217399023904840576646
      Line 125, in log /nightly/current_run/scratch/master/edn-sim-xcelium/1.edn_intr/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/edn-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_count_0/rtl/prim_count.sv,300): (time 7714498 PS) Assertion tb.dut.u_edn_core.u_prim_count_max_reqs_cntr.CntErrReported_A has failed (2 cycles, starting 7694498 PS)
        UVM_ERROR @   7714498 ps: (prim_count.sv:300) [ASSERT FAILED] CntErrReported_A
        UVM_INFO @   7714498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 4.edn_intr.77489898664180890350214542642343510622959665930947394691496286038191197891795
      Line 125, in log /nightly/current_run/scratch/master/edn-sim-xcelium/4.edn_intr/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/edn-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_count_0/rtl/prim_count.sv,300): (time 8520357 PS) Assertion tb.dut.u_edn_core.u_prim_count_max_reqs_cntr.CntErrReported_A has failed (2 cycles, starting 8499524 PS)
        UVM_ERROR @   8520357 ps: (prim_count.sv:300) [ASSERT FAILED] CntErrReported_A
        UVM_INFO @   8520357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 9 more failures.

• xmsim: *E,ASRTST (/nightly/current_run/scratch/master/edn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_edn_*/rtl/edn_ack_sm.sv,52): Assertion u_state_regs_A has failed has 36 failures:

  • Test edn_err has 27 failures.

    • 2.edn_err.54754459999307340928201450608198699607444160532032230017612978468978312599476
      Line 142, in log /nightly/current_run/scratch/master/edn-sim-xcelium/2.edn_err/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/edn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv,52): (time 23799668 PS) Assertion tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep.u_state_regs_A has failed
        UVM_ERROR @  23799668 ps: (edn_ack_sm.sv:52) [ASSERT FAILED] u_state_regs_A
        UVM_INFO @  23799668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 5.edn_err.102367682928382849733619929162840772795356492675941004093832354023861884524563
      Line 142, in log /nightly/current_run/scratch/master/edn-sim-xcelium/5.edn_err/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/edn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv,52): (time 14577582 PS) Assertion tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep.u_state_regs_A has failed
        UVM_ERROR @  14577582 ps: (edn_ack_sm.sv:52) [ASSERT FAILED] u_state_regs_A
        UVM_INFO @  14577582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 25 more failures.

  • Test edn_intr has 9 failures.

    • 6.edn_intr.45218159002090101526961430139219050628103131555160719605695403357728536995630
      Line 123, in log /nightly/current_run/scratch/master/edn-sim-xcelium/6.edn_intr/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/edn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv,52): (time 4822471 PS) Assertion tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep.u_state_regs_A has failed
        UVM_ERROR @   4822471 ps: (edn_ack_sm.sv:52) [ASSERT FAILED] u_state_regs_A
        UVM_INFO @   4822471 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 9.edn_intr.2100134787948856935391315431158557416925259782461769599018290240817035026782
      Line 123, in log /nightly/current_run/scratch/master/edn-sim-xcelium/9.edn_intr/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/edn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv,52): (time 23430987 PS) Assertion tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep.u_state_regs_A has failed
        UVM_ERROR @  23430987 ps: (edn_ack_sm.sv:52) [ASSERT FAILED] u_state_regs_A
        UVM_INFO @  23430987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 7 more failures.

• xmsim: *E,ASRTST (/nightly/current_run/scratch/master/edn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_edn_*/rtl/edn_main_sm.sv,42): Assertion u_state_regs_A has failed has 34 failures:

  • Test edn_intr has 8 failures.

    • 2.edn_intr.97977986843906881638053040562754728536470082409246892291147218712240463696918
      Line 123, in log /nightly/current_run/scratch/master/edn-sim-xcelium/2.edn_intr/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/edn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv,42): (time 28912263 PS) Assertion tb.dut.u_edn_core.u_edn_main_sm.u_state_regs_A has failed
        UVM_ERROR @  28912263 ps: (edn_main_sm.sv:42) [ASSERT FAILED] u_state_regs_A
        UVM_INFO @  28912263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 3.edn_intr.101178589847757277054287080879791146357097541457384692809171943497247851582023
      Line 123, in log /nightly/current_run/scratch/master/edn-sim-xcelium/3.edn_intr/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/edn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv,42): (time 35189683 PS) Assertion tb.dut.u_edn_core.u_edn_main_sm.u_state_regs_A has failed
        UVM_ERROR @  35189683 ps: (edn_main_sm.sv:42) [ASSERT FAILED] u_state_regs_A
        UVM_INFO @  35189683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 6 more failures.

  • Test edn_err has 26 failures.

    • 3.edn_err.24774317162595005862098160517406958553430947899935271488438983074591081520421
      Line 142, in log /nightly/current_run/scratch/master/edn-sim-xcelium/3.edn_err/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/edn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv,42): (time 50300864 PS) Assertion tb.dut.u_edn_core.u_edn_main_sm.u_state_regs_A has failed
        UVM_ERROR @  50300864 ps: (edn_main_sm.sv:42) [ASSERT FAILED] u_state_regs_A
        UVM_INFO @  50300864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 4.edn_err.9516878919365717163667694256301145620542738388395192230374747260257971526112
      Line 142, in log /nightly/current_run/scratch/master/edn-sim-xcelium/4.edn_err/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/edn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv,42): (time 5428245 PS) Assertion tb.dut.u_edn_core.u_edn_main_sm.u_state_regs_A has failed
        UVM_ERROR @   5428245 ps: (edn_main_sm.sv:42) [ASSERT FAILED] u_state_regs_A
        UVM_INFO @   5428245 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 24 more failures.

• Job timed out after * minutes has 20 failures:

  • Test edn_stress_all_with_rand_reset has 20 failures.

    • 1.edn_stress_all_with_rand_reset.105570931401742956777976591940130112623577221212083625231121415561359914414997
      Log /nightly/current_run/scratch/master/edn-sim-xcelium/1.edn_stress_all_with_rand_reset/latest/run.log

        Job timed out after 180 minutes
      

    • 3.edn_stress_all_with_rand_reset.62350297054479717465496888012257099011134511180351798665449954955433911544091
      Log /nightly/current_run/scratch/master/edn-sim-xcelium/3.edn_stress_all_with_rand_reset/latest/run.log

        Job timed out after 180 minutes
      

    • ... and 18 more failures.

• Job returned non-zero exit code has 1 failures:

  • Test edn has 1 failures.

    • cov_merge
      Log /nightly/current_run/scratch/master/edn-sim-xcelium/cov_merge/merged/cov_merge.log

        [Executing]:
        make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk cov_merge cov_merge_cmd=imc cov_merge_opts='-64bit -licqueue -exec /nightly/current_run/opentitan/hw/dv/tools/xcelium/cov_merge.tcl'
      
        [make]: cov_merge
        imc -64bit -licqueue -exec /nightly/current_run/opentitan/hw/dv/tools/xcelium/cov_merge.tcl
        *I,imc.tool.cov.version.diff: "There is a difference between the IMC tool version 22.09 and the coverage version 21.09-s006"
        Error: Cannot invoke "jdk.internal.platform.CgroupInfo.getMountPoint()" because "<parameter1>" is null
        Created log file /nightly/current_run/opentitan/startup.log
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:231: cov_merge] Error 1
      

• Job killed most likely because its dependent job failed. has 1 failures:

  • Test edn has 1 failures.
    • cov_report
      Log /nightly/current_run/scratch/master/edn-sim-xcelium/cov_report/cov_report.log