HMAC Simulation Results

Tuesday September 09 2025 00:00:40 UTC

GitHub Revision: 2144e83

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 17.000s 8.182ms 10 10 100.00
V1 csr_hw_reset hmac_csr_hw_reset 3.000s 65.142us 5 5 100.00
V1 csr_rw hmac_csr_rw 3.000s 16.425us 20 20 100.00
V1 csr_bit_bash hmac_csr_bit_bash 18.000s 1.067ms 5 5 100.00
V1 csr_aliasing hmac_csr_aliasing 10.000s 5.510ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 18.617m 83.679ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 3.000s 16.425us 20 20 100.00
hmac_csr_aliasing 10.000s 5.510ms 5 5 100.00
V1 TOTAL 65 65 100.00
V2 long_msg hmac_long_msg 2.033m 1.833ms 10 10 100.00
V2 back_pressure hmac_back_pressure 2.750m 7.836ms 25 25 100.00
V2 test_vectors hmac_test_sha256_vectors 6.867m 21.464ms 30 30 100.00
hmac_test_sha384_vectors 14.750m 56.256ms 75 75 100.00
hmac_test_sha512_vectors 13.650m 11.954ms 75 75 100.00
hmac_test_hmac256_vectors 25.000s 811.600us 50 50 100.00
hmac_test_hmac384_vectors 28.000s 370.902us 60 60 100.00
hmac_test_hmac512_vectors 29.000s 419.476us 75 75 100.00
V2 burst_wr hmac_burst_wr 53.000s 2.565ms 50 50 100.00
V2 datapath_stress hmac_datapath_stress 10.283m 8.391ms 10 10 100.00
V2 error hmac_error 2.500m 8.166ms 10 10 100.00
V2 wipe_secret hmac_wipe_secret 3.033m 45.390ms 10 10 100.00
V2 save_and_restore hmac_smoke 17.000s 8.182ms 10 10 100.00
hmac_long_msg 2.033m 1.833ms 10 10 100.00
hmac_back_pressure 2.750m 7.836ms 25 25 100.00
hmac_datapath_stress 10.283m 8.391ms 10 10 100.00
hmac_burst_wr 53.000s 2.565ms 50 50 100.00
hmac_stress_all 20.067m 185.520ms 50 50 100.00
V2 fifo_empty_status_interrupt hmac_smoke 17.000s 8.182ms 10 10 100.00
hmac_long_msg 2.033m 1.833ms 10 10 100.00
hmac_back_pressure 2.750m 7.836ms 25 25 100.00
hmac_datapath_stress 10.283m 8.391ms 10 10 100.00
hmac_wipe_secret 3.033m 45.390ms 10 10 100.00
hmac_test_sha256_vectors 6.867m 21.464ms 30 30 100.00
hmac_test_sha384_vectors 14.750m 56.256ms 75 75 100.00
hmac_test_sha512_vectors 13.650m 11.954ms 75 75 100.00
hmac_test_hmac256_vectors 25.000s 811.600us 50 50 100.00
hmac_test_hmac384_vectors 28.000s 370.902us 60 60 100.00
hmac_test_hmac512_vectors 29.000s 419.476us 75 75 100.00
V2 wide_digest_configurable_key_length hmac_smoke 17.000s 8.182ms 10 10 100.00
hmac_long_msg 2.033m 1.833ms 10 10 100.00
hmac_back_pressure 2.750m 7.836ms 25 25 100.00
hmac_datapath_stress 10.283m 8.391ms 10 10 100.00
hmac_burst_wr 53.000s 2.565ms 50 50 100.00
hmac_error 2.500m 8.166ms 10 10 100.00
hmac_wipe_secret 3.033m 45.390ms 10 10 100.00
hmac_test_sha256_vectors 6.867m 21.464ms 30 30 100.00
hmac_test_sha384_vectors 14.750m 56.256ms 75 75 100.00
hmac_test_sha512_vectors 13.650m 11.954ms 75 75 100.00
hmac_test_hmac256_vectors 25.000s 811.600us 50 50 100.00
hmac_test_hmac384_vectors 28.000s 370.902us 60 60 100.00
hmac_test_hmac512_vectors 29.000s 419.476us 75 75 100.00
hmac_stress_all 20.067m 185.520ms 50 50 100.00
V2 stress_all hmac_stress_all 20.067m 185.520ms 50 50 100.00
V2 alert_test hmac_alert_test 3.000s 17.335us 50 50 100.00
V2 intr_test hmac_intr_test 3.000s 15.932us 50 50 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 7.000s 1.061ms 20 20 100.00
V2 tl_d_illegal_access hmac_tl_errors 7.000s 1.061ms 20 20 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 3.000s 65.142us 5 5 100.00
hmac_csr_rw 3.000s 16.425us 20 20 100.00
hmac_csr_aliasing 10.000s 5.510ms 5 5 100.00
hmac_same_csr_outstanding 4.000s 144.686us 20 20 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 3.000s 65.142us 5 5 100.00
hmac_csr_rw 3.000s 16.425us 20 20 100.00
hmac_csr_aliasing 10.000s 5.510ms 5 5 100.00
hmac_same_csr_outstanding 4.000s 144.686us 20 20 100.00
V2 TOTAL 670 670 100.00
V2S tl_intg_err hmac_sec_cm 4.000s 94.513us 5 5 100.00
hmac_tl_intg_err 7.000s 223.469us 20 20 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 7.000s 223.469us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 17.000s 8.182ms 10 10 100.00
V3 stress_reset hmac_stress_reset 12.000s 160.225us 25 25 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 10.117m 28.274ms 35 35 100.00
V3 TOTAL 60 60 100.00
Unmapped tests hmac_directed 3.000s 18.864us 1 1 100.00
TOTAL 821 821 100.00

Failure Buckets