I2C Simulation Results

Tuesday September 09 2025 00:00:40 UTC

GitHub Revision: 2144e83

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 host_smoke i2c_host_smoke 0 50 0.00
V1 target_smoke i2c_target_smoke 33.000s 2.200ms 50 50 100.00
V1 csr_hw_reset i2c_csr_hw_reset 3.000s 59.897us 5 5 100.00
V1 csr_rw i2c_csr_rw 3.000s 23.443us 20 20 100.00
V1 csr_bit_bash i2c_csr_bit_bash 5.000s 120.741us 5 5 100.00
V1 csr_aliasing i2c_csr_aliasing 4.000s 414.329us 5 5 100.00
V1 csr_mem_rw_with_rand_reset i2c_csr_mem_rw_with_rand_reset 3.000s 21.242us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr i2c_csr_rw 3.000s 23.443us 20 20 100.00
i2c_csr_aliasing 4.000s 414.329us 5 5 100.00
V1 TOTAL 105 155 67.74
V2 host_error_intr i2c_host_error_intr 9.067m 150.470us 1 50 2.00
V2 host_stress_all i2c_host_stress_all 45.933m 600.000ms 0 50 0.00
V2 host_maxperf i2c_host_perf 57.067m 1.294ms 21 50 42.00
V2 host_override i2c_host_override 4.000s 28.232us 50 50 100.00
V2 host_fifo_watermark i2c_host_fifo_watermark 0 50 0.00
V2 host_fifo_overflow i2c_host_fifo_overflow 0 50 0.00
V2 host_fifo_reset i2c_host_fifo_reset_fmt 33.000s 177.297us 50 50 100.00
i2c_host_fifo_fmt_empty 49.000m 284.309us 10 50 20.00
i2c_host_fifo_reset_rx 59.683m 192.263us 32 50 64.00
V2 host_fifo_full i2c_host_fifo_full 1.467m 17.207ms 2 50 4.00
V2 host_timeout i2c_host_stretch_timeout 54.767m 850.036us 38 50 76.00
V2 i2c_host_mode_toggle i2c_host_mode_toggle 8.250m 104.435us 7 50 14.00
V2 target_glitch i2c_target_glitch 5.000s 702.551us 0 2 0.00
V2 target_stress_all i2c_target_stress_all 0 50 0.00
V2 target_maxperf i2c_target_perf 55.933m 752.599us 43 50 86.00
V2 target_fifo_empty i2c_target_stress_rd 46.800m 5.290ms 28 50 56.00
i2c_target_intr_smoke 44.933m 3.573ms 39 50 78.00
V2 target_fifo_reset i2c_target_fifo_reset_acq 17.517m 859.195us 50 50 100.00
i2c_target_fifo_reset_tx 50.133m 871.938us 50 50 100.00
V2 target_fifo_full i2c_target_stress_wr 27.933m 32.057ms 22 50 44.00
i2c_target_stress_rd 46.800m 5.290ms 28 50 56.00
i2c_target_intr_stress_wr 58.000s 7.634ms 7 50 14.00
V2 target_timeout i2c_target_timeout 59.933m 1.436ms 28 50 56.00
V2 target_clock_stretch i2c_target_stretch 49.133m 1.243ms 9 50 18.00
V2 bad_address i2c_target_bad_addr 15.700m 18.090ms 49 50 98.00
V2 target_mode_glitch i2c_target_hrst 1.217m 10.168ms 22 50 44.00
V2 target_fifo_watermark i2c_target_fifo_watermarks_acq 42.000s 673.222us 50 50 100.00
i2c_target_fifo_watermarks_tx 5.000s 591.677us 48 50 96.00
V2 host_mode_config_perf i2c_host_perf 57.067m 1.294ms 21 50 42.00
i2c_host_perf_precise 55.783m 1.101ms 38 50 76.00
V2 host_mode_clock_stretching i2c_host_stretch_timeout 54.767m 850.036us 38 50 76.00
V2 target_mode_tx_stretch_ctrl i2c_target_tx_stretch_ctrl 11.000s 638.765us 47 50 94.00
V2 target_mode_nack_generation i2c_target_nack_acqfull 11.000s 2.244ms 50 50 100.00
i2c_target_nack_acqfull_addr 30.000s 538.939us 50 50 100.00
i2c_target_nack_txstretch 39.267m 758.149us 50 50 100.00
V2 host_mode_halt_on_nak i2c_host_may_nack 38.000s 740.661us 50 50 100.00
V2 target_mode_smbus_maxlen i2c_target_smbus_maxlen 7.000s 402.628us 50 50 100.00
V2 alert_test i2c_alert_test 6.000s 51.368us 50 50 100.00
V2 intr_test i2c_intr_test 3.000s 46.594us 50 50 100.00
V2 tl_d_oob_addr_access i2c_tl_errors 4.000s 100.896us 20 20 100.00
V2 tl_d_illegal_access i2c_tl_errors 4.000s 100.896us 20 20 100.00
V2 tl_d_outstanding_access i2c_csr_hw_reset 3.000s 59.897us 5 5 100.00
i2c_csr_rw 3.000s 23.443us 20 20 100.00
i2c_csr_aliasing 4.000s 414.329us 5 5 100.00
i2c_same_csr_outstanding 3.000s 28.109us 19 20 95.00
V2 tl_d_partial_access i2c_csr_hw_reset 3.000s 59.897us 5 5 100.00
i2c_csr_rw 3.000s 23.443us 20 20 100.00
i2c_csr_aliasing 4.000s 414.329us 5 5 100.00
i2c_same_csr_outstanding 3.000s 28.109us 19 20 95.00
V2 TOTAL 1130 1792 63.06
V2S tl_intg_err i2c_tl_intg_err 4.000s 446.063us 20 20 100.00
i2c_sec_cm 3.000s 68.556us 5 5 100.00
V2S sec_cm_bus_integrity i2c_tl_intg_err 4.000s 446.063us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 host_stress_all_with_rand_reset i2c_host_stress_all_with_rand_reset 2.600m 268.830us 0 10 0.00
V3 target_error_intr i2c_target_unexp_stop 29.000m 9.722ms 0 50 0.00
V3 target_stress_all_with_rand_reset i2c_target_stress_all_with_rand_reset 2.033m 445.683us 0 10 0.00
V3 TOTAL 0 70 0.00
TOTAL 1260 2042 61.70

Failure Buckets