KMAC/MASKED Simulation Results

Tuesday September 09 2025 00:00:40 UTC

GitHub Revision: 2144e83

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke kmac_smoke 2.700m 18.125ms 0 50 0.00
V1 csr_hw_reset kmac_csr_hw_reset 4.000s 36.442us 0 5 0.00
V1 csr_rw kmac_csr_rw 4.000s 249.140us 0 20 0.00
V1 csr_bit_bash kmac_csr_bit_bash 25.000s 294.273us 0 5 0.00
V1 csr_aliasing kmac_csr_aliasing 13.000s 439.246us 0 5 0.00
V1 csr_mem_rw_with_rand_reset kmac_csr_mem_rw_with_rand_reset 6.000s 105.867us 0 20 0.00
V1 regwen_csr_and_corresponding_lockable_csr kmac_csr_rw 4.000s 249.140us 0 20 0.00
kmac_csr_aliasing 13.000s 439.246us 0 5 0.00
V1 mem_walk kmac_mem_walk 3.000s 23.999us 0 5 0.00
V1 mem_partial_access kmac_mem_partial_access 4.000s 85.842us 0 5 0.00
V1 TOTAL 0 115 0.00
V2 long_msg_and_output kmac_long_msg_and_output 1.387h 127.504ms 0 50 0.00
V2 burst_write kmac_burst_write 34.317m 35.406ms 0 50 0.00
V2 test_vectors kmac_test_vectors_sha3_224 49.267m 260.526ms 0 5 0.00
kmac_test_vectors_sha3_256 45.667m 116.086ms 0 5 0.00
kmac_test_vectors_sha3_384 35.933m 235.355ms 0 5 0.00
kmac_test_vectors_sha3_512 24.317m 50.412ms 0 5 0.00
kmac_test_vectors_shake_128 1.037h 106.756ms 0 5 0.00
kmac_test_vectors_shake_256 41.517m 366.808ms 0 5 0.00
kmac_test_vectors_kmac 9.000s 380.298us 0 5 0.00
kmac_test_vectors_kmac_xof 8.000s 95.230us 0 5 0.00
V2 sideload kmac_sideload 11.267m 263.230ms 0 50 0.00
V2 app kmac_app 7.050m 22.933ms 0 50 0.00
V2 app_with_partial_data kmac_app_with_partial_data 6.950m 56.247ms 0 10 0.00
V2 entropy_refresh kmac_entropy_refresh 7.550m 32.230ms 0 50 0.00
V2 error kmac_error 10.600m 18.989ms 0 50 0.00
V2 key_error kmac_key_error 28.000s 10.172ms 0 50 0.00
V2 sideload_invalid kmac_sideload_invalid 14.000s 460.204us 0 50 0.00
V2 edn_timeout_error kmac_edn_timeout_error 5.000s 0 20 0.00
V2 entropy_mode_error kmac_entropy_mode_error 3.000s 0 20 0.00
V2 entropy_ready_error kmac_entropy_ready_error 2.050m 131.070ms 0 10 0.00
V2 lc_escalation kmac_lc_escalation 12.650m 10.512ms 0 50 0.00
V2 stress_all kmac_stress_all 1.080h 34.601ms 0 50 0.00
V2 intr_test kmac_intr_test 4.000s 57.182us 0 50 0.00
V2 alert_test kmac_alert_test 4.000s 103.531us 0 50 0.00
V2 tl_d_oob_addr_access kmac_tl_errors 7.000s 261.433us 0 20 0.00
V2 tl_d_illegal_access kmac_tl_errors 7.000s 261.433us 0 20 0.00
V2 tl_d_outstanding_access kmac_csr_hw_reset 4.000s 36.442us 0 5 0.00
kmac_csr_rw 4.000s 249.140us 0 20 0.00
kmac_csr_aliasing 13.000s 439.246us 0 5 0.00
kmac_same_csr_outstanding 6.000s 442.524us 0 20 0.00
V2 tl_d_partial_access kmac_csr_hw_reset 4.000s 36.442us 0 5 0.00
kmac_csr_rw 4.000s 249.140us 0 20 0.00
kmac_csr_aliasing 13.000s 439.246us 0 5 0.00
kmac_same_csr_outstanding 6.000s 442.524us 0 20 0.00
V2 TOTAL 0 740 0.00
V2S shadow_reg_update_error kmac_shadow_reg_errors 5.000s 104.620us 0 20 0.00
V2S shadow_reg_read_clear_staged_value kmac_shadow_reg_errors 5.000s 104.620us 0 20 0.00
V2S shadow_reg_storage_error kmac_shadow_reg_errors 5.000s 104.620us 0 20 0.00
V2S shadowed_reset_glitch kmac_shadow_reg_errors 5.000s 104.620us 0 20 0.00
V2S shadow_reg_update_error_with_csr_rw kmac_shadow_reg_errors_with_csr_rw 10.000s 872.347us 0 20 0.00
V2S tl_intg_err kmac_sec_cm 3.367m 13.635ms 0 5 0.00
kmac_tl_intg_err 10.000s 1.069ms 0 20 0.00
V2S sec_cm_bus_integrity kmac_tl_intg_err 10.000s 1.069ms 0 20 0.00
V2S sec_cm_lc_escalate_en_intersig_mubi kmac_lc_escalation 12.650m 10.512ms 0 50 0.00
V2S sec_cm_sw_key_key_masking kmac_smoke 2.700m 18.125ms 0 50 0.00
V2S sec_cm_key_sideload kmac_sideload 11.267m 263.230ms 0 50 0.00
V2S sec_cm_cfg_shadowed_config_shadow kmac_shadow_reg_errors 5.000s 104.620us 0 20 0.00
V2S sec_cm_fsm_sparse kmac_sec_cm 3.367m 13.635ms 0 5 0.00
V2S sec_cm_ctr_redun kmac_sec_cm 3.367m 13.635ms 0 5 0.00
V2S sec_cm_packer_ctr_redun kmac_sec_cm 3.367m 13.635ms 0 5 0.00
V2S sec_cm_cfg_shadowed_config_regwen kmac_smoke 2.700m 18.125ms 0 50 0.00
V2S sec_cm_fsm_global_esc kmac_lc_escalation 12.650m 10.512ms 0 50 0.00
V2S sec_cm_fsm_local_esc kmac_sec_cm 3.367m 13.635ms 0 5 0.00
V2S sec_cm_absorbed_ctrl_mubi kmac_mubi 7.450m 22.055ms 0 10 0.00
V2S sec_cm_sw_cmd_ctrl_sparse kmac_smoke 2.700m 18.125ms 0 50 0.00
V2S TOTAL 0 75 0.00
V3 stress_all_with_rand_reset kmac_stress_all_with_rand_reset 6.267m 4.004ms 0 10 0.00
V3 TOTAL 0 10 0.00
TOTAL 0 940 0.00

Failure Buckets