KMAC/UNMASKED Simulation Results

Tuesday September 09 2025 00:00:40 UTC

GitHub Revision: 2144e83

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke kmac_smoke 1.933m 14.618ms 0 50 0.00
V1 csr_hw_reset kmac_csr_hw_reset 4.000s 50.455us 0 5 0.00
V1 csr_rw kmac_csr_rw 4.000s 106.465us 0 20 0.00
V1 csr_bit_bash kmac_csr_bit_bash 29.000s 1.263ms 0 5 0.00
V1 csr_aliasing kmac_csr_aliasing 13.000s 1.130ms 0 5 0.00
V1 csr_mem_rw_with_rand_reset kmac_csr_mem_rw_with_rand_reset 6.000s 140.957us 0 20 0.00
V1 regwen_csr_and_corresponding_lockable_csr kmac_csr_rw 4.000s 106.465us 0 20 0.00
kmac_csr_aliasing 13.000s 1.130ms 0 5 0.00
V1 mem_walk kmac_mem_walk 4.000s 84.124us 0 5 0.00
V1 mem_partial_access kmac_mem_partial_access 4.000s 109.728us 0 5 0.00
V1 TOTAL 0 115 0.00
V2 long_msg_and_output kmac_long_msg_and_output 1.179h 263.096ms 0 50 0.00
V2 burst_write kmac_burst_write 25.050m 36.468ms 0 50 0.00
V2 test_vectors kmac_test_vectors_sha3_224 37.367m 118.114ms 0 5 0.00
kmac_test_vectors_sha3_256 42.133m 174.657ms 0 5 0.00
kmac_test_vectors_sha3_384 30.500m 67.276ms 0 5 0.00
kmac_test_vectors_sha3_512 19.600m 188.018ms 0 5 0.00
kmac_test_vectors_shake_128 49.533m 108.122ms 0 5 0.00
kmac_test_vectors_shake_256 38.017m 270.620ms 0 5 0.00
kmac_test_vectors_kmac 5.000s 85.520us 0 5 0.00
kmac_test_vectors_kmac_xof 5.000s 220.235us 0 5 0.00
V2 sideload kmac_sideload 8.650m 25.059ms 0 50 0.00
V2 app kmac_app 6.783m 236.264ms 0 50 0.00
V2 app_with_partial_data kmac_app_with_partial_data 2.767m 6.633ms 0 10 0.00
V2 entropy_refresh kmac_entropy_refresh 7.717m 19.453ms 0 50 0.00
V2 error kmac_error 8.767m 34.668ms 0 50 0.00
V2 key_error kmac_key_error 30.000s 29.596ms 0 50 0.00
V2 sideload_invalid kmac_sideload_invalid 4.017m 10.061ms 0 50 0.00
V2 edn_timeout_error kmac_edn_timeout_error 17.000s 0 20 0.00
V2 entropy_mode_error kmac_entropy_mode_error 14.000s 0 20 0.00
V2 entropy_ready_error kmac_entropy_ready_error 1.583m 6.829ms 0 10 0.00
V2 lc_escalation kmac_lc_escalation 8.950m 10.006ms 0 50 0.00
V2 stress_all kmac_stress_all 57.733m 127.829ms 0 50 0.00
V2 intr_test kmac_intr_test 3.000s 15.646us 0 50 0.00
V2 alert_test kmac_alert_test 4.000s 140.780us 0 50 0.00
V2 tl_d_oob_addr_access kmac_tl_errors 7.000s 870.100us 0 20 0.00
V2 tl_d_illegal_access kmac_tl_errors 7.000s 870.100us 0 20 0.00
V2 tl_d_outstanding_access kmac_csr_hw_reset 4.000s 50.455us 0 5 0.00
kmac_csr_rw 4.000s 106.465us 0 20 0.00
kmac_csr_aliasing 13.000s 1.130ms 0 5 0.00
kmac_same_csr_outstanding 6.000s 834.469us 0 20 0.00
V2 tl_d_partial_access kmac_csr_hw_reset 4.000s 50.455us 0 5 0.00
kmac_csr_rw 4.000s 106.465us 0 20 0.00
kmac_csr_aliasing 13.000s 1.130ms 0 5 0.00
kmac_same_csr_outstanding 6.000s 834.469us 0 20 0.00
V2 TOTAL 0 740 0.00
V2S shadow_reg_update_error kmac_shadow_reg_errors 5.000s 1.253ms 0 20 0.00
V2S shadow_reg_read_clear_staged_value kmac_shadow_reg_errors 5.000s 1.253ms 0 20 0.00
V2S shadow_reg_storage_error kmac_shadow_reg_errors 5.000s 1.253ms 0 20 0.00
V2S shadowed_reset_glitch kmac_shadow_reg_errors 5.000s 1.253ms 0 20 0.00
V2S shadow_reg_update_error_with_csr_rw kmac_shadow_reg_errors_with_csr_rw 9.000s 457.375us 0 20 0.00
V2S tl_intg_err kmac_sec_cm 1.767m 8.632ms 0 5 0.00
kmac_tl_intg_err 10.000s 452.730us 0 20 0.00
V2S sec_cm_bus_integrity kmac_tl_intg_err 10.000s 452.730us 0 20 0.00
V2S sec_cm_lc_escalate_en_intersig_mubi kmac_lc_escalation 8.950m 10.006ms 0 50 0.00
V2S sec_cm_sw_key_key_masking kmac_smoke 1.933m 14.618ms 0 50 0.00
V2S sec_cm_key_sideload kmac_sideload 8.650m 25.059ms 0 50 0.00
V2S sec_cm_cfg_shadowed_config_shadow kmac_shadow_reg_errors 5.000s 1.253ms 0 20 0.00
V2S sec_cm_fsm_sparse kmac_sec_cm 1.767m 8.632ms 0 5 0.00
V2S sec_cm_ctr_redun kmac_sec_cm 1.767m 8.632ms 0 5 0.00
V2S sec_cm_packer_ctr_redun kmac_sec_cm 1.767m 8.632ms 0 5 0.00
V2S sec_cm_cfg_shadowed_config_regwen kmac_smoke 1.933m 14.618ms 0 50 0.00
V2S sec_cm_fsm_global_esc kmac_lc_escalation 8.950m 10.006ms 0 50 0.00
V2S sec_cm_fsm_local_esc kmac_sec_cm 1.767m 8.632ms 0 5 0.00
V2S sec_cm_absorbed_ctrl_mubi kmac_mubi 8.000m 36.136ms 0 10 0.00
V2S sec_cm_sw_cmd_ctrl_sparse kmac_smoke 1.933m 14.618ms 0 50 0.00
V2S TOTAL 0 75 0.00
V3 stress_all_with_rand_reset kmac_stress_all_with_rand_reset 8.217m 20.484ms 0 10 0.00
V3 TOTAL 0 10 0.00
TOTAL 0 940 0.00

Failure Buckets