OTBN Simulation Results

Tuesday September 09 2025 00:00:40 UTC

GitHub Revision: 2144e83

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke otbn_smoke 15.000s 132.437us 0 1 0.00
V1 single_binary otbn_single 1.550m 336.813us 0 100 0.00
V1 csr_hw_reset otbn_csr_hw_reset 9.000s 31.336us 5 5 100.00
V1 csr_rw otbn_csr_rw 9.000s 32.441us 20 20 100.00
V1 csr_bit_bash otbn_csr_bit_bash 7.000s 102.846us 5 5 100.00
V1 csr_aliasing otbn_csr_aliasing 5.000s 29.187us 5 5 100.00
V1 csr_mem_rw_with_rand_reset otbn_csr_mem_rw_with_rand_reset 14.000s 45.977us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr otbn_csr_rw 9.000s 32.441us 20 20 100.00
otbn_csr_aliasing 5.000s 29.187us 5 5 100.00
V1 mem_walk otbn_mem_walk 58.000s 8.496ms 5 5 100.00
V1 mem_partial_access otbn_mem_partial_access 27.000s 1.997ms 5 5 100.00
V1 TOTAL 65 166 39.16
V2 reset_recovery otbn_reset 45.000s 813.502us 0 10 0.00
V2 multi_error otbn_multi_err 1.633m 222.549us 0 1 0.00
V2 back_to_back otbn_multi 1.917m 312.170us 0 10 0.00
V2 stress_all otbn_stress_all 2.600m 699.943us 0 10 0.00
V2 lc_escalation otbn_escalate 38.000s 106.136us 19 60 31.67
V2 zero_state_err_urnd otbn_zero_state_err_urnd 14.000s 41.599us 4 5 80.00
V2 sw_errs_fatal_chk otbn_sw_errs_fatal_chk 29.000s 78.862us 0 10 0.00
V2 alert_test otbn_alert_test 8.000s 28.270us 50 50 100.00
V2 intr_test otbn_intr_test 7.000s 13.420us 50 50 100.00
V2 tl_d_oob_addr_access otbn_tl_errors 12.000s 46.403us 20 20 100.00
V2 tl_d_illegal_access otbn_tl_errors 12.000s 46.403us 20 20 100.00
V2 tl_d_outstanding_access otbn_csr_hw_reset 9.000s 31.336us 5 5 100.00
otbn_csr_rw 9.000s 32.441us 20 20 100.00
otbn_csr_aliasing 5.000s 29.187us 5 5 100.00
otbn_same_csr_outstanding 7.000s 89.333us 20 20 100.00
V2 tl_d_partial_access otbn_csr_hw_reset 9.000s 31.336us 5 5 100.00
otbn_csr_rw 9.000s 32.441us 20 20 100.00
otbn_csr_aliasing 5.000s 29.187us 5 5 100.00
otbn_same_csr_outstanding 7.000s 89.333us 20 20 100.00
V2 TOTAL 163 246 66.26
V2S mem_integrity otbn_imem_err 13.000s 28.131us 0 10 0.00
otbn_dmem_err 16.000s 46.867us 0 15 0.00
V2S internal_integrity otbn_alu_bignum_mod_err 1.150m 759.808us 0 5 0.00
otbn_controller_ispr_rdata_err 19.000s 85.679us 0 5 0.00
otbn_mac_bignum_acc_err 13.000s 58.435us 0 5 0.00
otbn_urnd_err 12.000s 20.527us 0 2 0.00
V2S illegal_bus_access otbn_illegal_mem_acc 9.000s 18.364us 5 5 100.00
V2S otbn_mem_gnt_acc_err otbn_mem_gnt_acc_err 9.000s 21.164us 2 2 100.00
V2S otbn_non_sec_partial_wipe otbn_partial_wipe 10.000s 27.099us 8 10 80.00
V2S tl_intg_err otbn_sec_cm 19.350m 5.138ms 4 5 80.00
otbn_tl_intg_err 1.583m 475.583us 20 20 100.00
V2S passthru_mem_tl_intg_err otbn_passthru_mem_tl_intg_err 44.000s 224.925us 11 20 55.00
V2S prim_fsm_check otbn_sec_cm 19.350m 5.138ms 4 5 80.00
V2S prim_count_check otbn_sec_cm 19.350m 5.138ms 4 5 80.00
V2S sec_cm_mem_scramble otbn_smoke 15.000s 132.437us 0 1 0.00
V2S sec_cm_data_mem_integrity otbn_dmem_err 16.000s 46.867us 0 15 0.00
V2S sec_cm_instruction_mem_integrity otbn_imem_err 13.000s 28.131us 0 10 0.00
V2S sec_cm_bus_integrity otbn_tl_intg_err 1.583m 475.583us 20 20 100.00
V2S sec_cm_controller_fsm_global_esc otbn_escalate 38.000s 106.136us 19 60 31.67
V2S sec_cm_controller_fsm_local_esc otbn_imem_err 13.000s 28.131us 0 10 0.00
otbn_dmem_err 16.000s 46.867us 0 15 0.00
otbn_zero_state_err_urnd 14.000s 41.599us 4 5 80.00
otbn_illegal_mem_acc 9.000s 18.364us 5 5 100.00
otbn_sec_cm 19.350m 5.138ms 4 5 80.00
V2S sec_cm_controller_fsm_sparse otbn_sec_cm 19.350m 5.138ms 4 5 80.00
V2S sec_cm_scramble_key_sideload otbn_single 1.550m 336.813us 0 100 0.00
V2S sec_cm_scramble_ctrl_fsm_local_esc otbn_imem_err 13.000s 28.131us 0 10 0.00
otbn_dmem_err 16.000s 46.867us 0 15 0.00
otbn_zero_state_err_urnd 14.000s 41.599us 4 5 80.00
otbn_illegal_mem_acc 9.000s 18.364us 5 5 100.00
otbn_sec_cm 19.350m 5.138ms 4 5 80.00
V2S sec_cm_scramble_ctrl_fsm_sparse otbn_sec_cm 19.350m 5.138ms 4 5 80.00
V2S sec_cm_start_stop_ctrl_fsm_global_esc otbn_escalate 38.000s 106.136us 19 60 31.67
V2S sec_cm_start_stop_ctrl_fsm_local_esc otbn_imem_err 13.000s 28.131us 0 10 0.00
otbn_dmem_err 16.000s 46.867us 0 15 0.00
otbn_zero_state_err_urnd 14.000s 41.599us 4 5 80.00
otbn_illegal_mem_acc 9.000s 18.364us 5 5 100.00
otbn_sec_cm 19.350m 5.138ms 4 5 80.00
V2S sec_cm_start_stop_ctrl_fsm_sparse otbn_sec_cm 19.350m 5.138ms 4 5 80.00
V2S sec_cm_data_reg_sw_sca otbn_single 1.550m 336.813us 0 100 0.00
V2S sec_cm_ctrl_redun otbn_ctrl_redun 16.000s 47.563us 0 12 0.00
V2S sec_cm_pc_ctrl_flow_redun otbn_pc_ctrl_flow_redun 11.000s 22.089us 5 5 100.00
V2S sec_cm_rnd_bus_consistency otbn_rnd_sec_cm 43.000s 1.107ms 0 5 0.00
V2S sec_cm_rnd_rng_digest otbn_rnd_sec_cm 43.000s 1.107ms 0 5 0.00
V2S sec_cm_rf_base_data_reg_sw_integrity otbn_rf_base_intg_err 16.000s 292.364us 0 10 0.00
V2S sec_cm_rf_base_data_reg_sw_glitch_detect otbn_sec_cm 19.350m 5.138ms 4 5 80.00
V2S sec_cm_stack_wr_ptr_ctr_redun otbn_sec_cm 19.350m 5.138ms 4 5 80.00
V2S sec_cm_rf_bignum_data_reg_sw_integrity otbn_rf_bignum_intg_err 15.000s 65.845us 0 10 0.00
V2S sec_cm_rf_bignum_data_reg_sw_glitch_detect otbn_sec_cm 19.350m 5.138ms 4 5 80.00
V2S sec_cm_loop_stack_ctr_redun otbn_sec_cm 19.350m 5.138ms 4 5 80.00
V2S sec_cm_loop_stack_addr_integrity otbn_stack_addr_integ_chk 36.000s 352.033us 0 5 0.00
V2S sec_cm_call_stack_addr_integrity otbn_stack_addr_integ_chk 36.000s 352.033us 0 5 0.00
V2S sec_cm_start_stop_ctrl_state_consistency otbn_sec_wipe_err 17.000s 56.394us 3 7 42.86
V2S sec_cm_data_mem_sec_wipe otbn_single 1.550m 336.813us 0 100 0.00
V2S sec_cm_instruction_mem_sec_wipe otbn_single 1.550m 336.813us 0 100 0.00
V2S sec_cm_data_reg_sw_sec_wipe otbn_single 1.550m 336.813us 0 100 0.00
V2S sec_cm_write_mem_integrity otbn_multi 1.917m 312.170us 0 10 0.00
V2S sec_cm_ctrl_flow_count otbn_single 1.550m 336.813us 0 100 0.00
V2S sec_cm_ctrl_flow_sca otbn_single 1.550m 336.813us 0 100 0.00
V2S sec_cm_data_mem_sw_noaccess otbn_sw_no_acc 1.117m 1.100ms 0 5 0.00
V2S sec_cm_key_sideload otbn_single 1.550m 336.813us 0 100 0.00
V2S sec_cm_tlul_fifo_ctr_redun otbn_sec_cm 19.350m 5.138ms 4 5 80.00
V2S TOTAL 58 163 35.58
V3 stress_all_with_rand_reset otbn_stress_all_with_rand_reset 7.983m 6.757ms 0 10 0.00
V3 TOTAL 0 10 0.00
TOTAL 286 585 48.89

Failure Buckets