2144e83| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pattgen_smoke | 7.000s | 631.843us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pattgen_csr_hw_reset | 3.000s | 59.234us | 5 | 5 | 100.00 |
| V1 | csr_rw | pattgen_csr_rw | 3.000s | 23.568us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pattgen_csr_bit_bash | 5.000s | 749.904us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pattgen_csr_aliasing | 3.000s | 165.601us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pattgen_csr_mem_rw_with_rand_reset | 4.000s | 52.669us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pattgen_csr_rw | 3.000s | 23.568us | 20 | 20 | 100.00 |
| pattgen_csr_aliasing | 3.000s | 165.601us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | perf | pattgen_perf | 49.600m | 600.000ms | 32 | 50 | 64.00 |
| V2 | cnt_rollover | cnt_rollover | 1.133m | 8.654ms | 50 | 50 | 100.00 |
| V2 | error | pattgen_error | 4.000s | 112.909us | 49 | 50 | 98.00 |
| V2 | stress_all | pattgen_stress_all | 1.951h | 10.000s | 22 | 50 | 44.00 |
| V2 | alert_test | pattgen_alert_test | 4.000s | 12.842us | 50 | 50 | 100.00 |
| V2 | intr_test | pattgen_intr_test | 3.000s | 24.005us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pattgen_tl_errors | 5.000s | 140.342us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pattgen_tl_errors | 5.000s | 140.342us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pattgen_csr_hw_reset | 3.000s | 59.234us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 3.000s | 23.568us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 3.000s | 165.601us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 3.000s | 22.176us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pattgen_csr_hw_reset | 3.000s | 59.234us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 3.000s | 23.568us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 3.000s | 165.601us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 3.000s | 22.176us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 293 | 340 | 86.18 | |||
| V2S | tl_intg_err | pattgen_tl_intg_err | 4.000s | 88.204us | 20 | 20 | 100.00 |
| pattgen_sec_cm | 3.000s | 107.163us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pattgen_tl_intg_err | 4.000s | 88.204us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | pattgen_stress_all_with_rand_reset | 1.900m | 4.572ms | 1 | 50 | 2.00 |
| V3 | TOTAL | 1 | 50 | 2.00 | |||
| Unmapped tests | pattgen_inactive_level | 2.167m | 10.003ms | 35 | 50 | 70.00 | |
| TOTAL | 459 | 570 | 80.53 |
UVM_ERROR (cip_base_vseq.sv:946) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 48 failures:
0.pattgen_stress_all_with_rand_reset.28096831798458065859754032203475225721236288489396133508893777283860873799062
Line 219, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 6473080167 ps: (cip_base_vseq.sv:946) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 6473113928 ps: (cip_base_vseq.sv:850) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 6473113928 ps: (cip_base_vseq.sv:853) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 4/5
UVM_INFO @ 6473280596 ps: (cip_base_vseq.sv:874) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
1.pattgen_stress_all_with_rand_reset.18568562856904642290703286232637385972187582841328398045141095268021798846748
Line 116, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 305497709 ps: (cip_base_vseq.sv:946) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 305500240 ps: (cip_base_vseq.sv:850) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 305500240 ps: (cip_base_vseq.sv:853) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 305531818 ps: (cip_base_vseq.sv:874) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
... and 46 more failures.
Job timed out after * minutes has 28 failures:
1.pattgen_perf.48342939805367975688992834969346159773978653545906753475809203008971644590375
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/1.pattgen_perf/latest/run.log
Job timed out after 60 minutes
9.pattgen_perf.36008592174488115030928650141197160294386938578293293414818269183904298675074
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/9.pattgen_perf/latest/run.log
Job timed out after 60 minutes
... and 11 more failures.
3.pattgen_stress_all.22014957669206180618983716222157013704658674971937869371302186414934949600244
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/3.pattgen_stress_all/latest/run.log
Job timed out after 180 minutes
4.pattgen_stress_all.110498112041293604338226114567976521558175183004052144941435812016169448816845
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/4.pattgen_stress_all/latest/run.log
Job timed out after 180 minutes
... and 13 more failures.
UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: has 11 failures:
0.pattgen_stress_all.93534513274062838107274228496772044207521557566183385105139371275891359269634
Line 122, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all/latest/run.log
UVM_ERROR @ 23274233377 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
--------------------------------------
Name Type Size Value
--------------------------------------
exp_item pattgen_item - @17420
6.pattgen_stress_all.70657058530706033780877884195789321582609235337034092754000259446640997390994
Line 144, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/6.pattgen_stress_all/latest/run.log
UVM_ERROR @ 2934512498 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10392
... and 9 more failures.
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 6 failures:
Test pattgen_stress_all has 1 failures.
7.pattgen_stress_all.92715023737737527623725856989569020190565548484060809901261820217728320546277
Line 122, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/7.pattgen_stress_all/latest/run.log
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test pattgen_perf has 5 failures.
22.pattgen_perf.16719912270016713710915024928677460804144675971325216667861483375448483291236
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/22.pattgen_perf/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
24.pattgen_perf.99196603168555684121979244127620709766788250585932782097011134272505787809266
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/24.pattgen_perf/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) has 3 failures:
2.pattgen_inactive_level.69070230956456923238708525411505584229302842229205042920931600981586764857579
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/2.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10006525024 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xdb1a1e90, Comparison=CompareOpEq, exp_data=0x0, call_count=5)
UVM_INFO @ 10006525024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
23.pattgen_inactive_level.30931572223165354317922351602139976348786279533595795843399352143313556870868
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/23.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10163504323 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x8410a50, Comparison=CompareOpEq, exp_data=0x0, call_count=5)
UVM_INFO @ 10163504323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (pattgen_scoreboard.sv:263) scoreboard [scoreboard] has 3 failures:
Test pattgen_error has 1 failures.
7.pattgen_error.9399226552216273053841294194781897887819868860762079185975063910474529495635
Line 98, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/7.pattgen_error/latest/run.log
UVM_ERROR @ 64222853 ps: (pattgen_scoreboard.sv:263) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
--> channel 1 item mismatch!
--> EXP:
------------------------------------
Name Type Size Value
Test pattgen_stress_all_with_rand_reset has 1 failures.
38.pattgen_stress_all_with_rand_reset.76833008275289177830115103231844290971393805511673214900022434489160611742577
Line 117, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/38.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 96204436 ps: (pattgen_scoreboard.sv:263) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
--> channel 0 item mismatch!
--> EXP:
------------------------------------
Name Type Size Value
Test pattgen_stress_all has 1 failures.
41.pattgen_stress_all.50704735746201205516162854116279122875081398363656471455499566130611366640776
Line 120, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/41.pattgen_stress_all/latest/run.log
UVM_ERROR @ 78462034 ps: (pattgen_scoreboard.sv:263) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
--> channel 1 item mismatch!
--> EXP:
------------------------------------
Name Type Size Value
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 2 failures:
31.pattgen_inactive_level.55269612624413335790489922803402501583885443171230865030352028460600359074746
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/31.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10026771405 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x691d1dd0, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 10026771405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
47.pattgen_inactive_level.1559269287063595795369553019174156643509541319647755636753204509940253355397
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/47.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10048107730 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x91f1d210, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 10048107730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 1 failures:
4.pattgen_inactive_level.27377912975876280193465590754331156376497842766908878865719747568433935053988
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/4.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10107537136 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0xd440fbd0, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 10107537136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 1 failures:
13.pattgen_inactive_level.99845854645042930256567429461474816534098385733432144169887828237636948619152
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/13.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10027728457 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x39c5cf10, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
UVM_INFO @ 10027728457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=20) has 1 failures:
14.pattgen_inactive_level.77617843290786402478480188281099230365283645370576119634857246787277123949173
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/14.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10036491079 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x434c8350, Comparison=CompareOpEq, exp_data=0x0, call_count=20)
UVM_INFO @ 10036491079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=14) has 1 failures:
15.pattgen_inactive_level.23038380661188765924972897221822257652736839667565451488723393036113642219666
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/15.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10058406853 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x20311550, Comparison=CompareOpEq, exp_data=0x0, call_count=14)
UVM_INFO @ 10058406853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4) has 1 failures:
20.pattgen_inactive_level.70264995503911729409636511143103048445064049518817688769527583446003835749743
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/20.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10006560972 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0xc9c8fc50, Comparison=CompareOpEq, exp_data=0x0, call_count=4)
UVM_INFO @ 10006560972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 1 failures:
25.pattgen_inactive_level.26805695253535618766615849339378669866160324371894539190319907552352416340939
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/25.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10047639574 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xa64a9550, Comparison=CompareOpEq, exp_data=0x0, call_count=13)
UVM_INFO @ 10047639574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) has 1 failures:
27.pattgen_inactive_level.15990466216391565561005025015118688285472518248135228540485331527378820631201
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/27.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10012339531 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0xbbe13290, Comparison=CompareOpEq, exp_data=0x0, call_count=6)
UVM_INFO @ 10012339531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 1 failures:
32.pattgen_inactive_level.4690029617886639075549432497314278568706154012203970258473331747814282315037
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/32.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10021554044 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x7707eed0, Comparison=CompareOpEq, exp_data=0x0, call_count=10)
UVM_INFO @ 10021554044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) has 1 failures:
34.pattgen_inactive_level.101490930572513631049156342328328216631700067714170080869397706496881544297544
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/34.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10100096325 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x5993e590, Comparison=CompareOpEq, exp_data=0x0, call_count=15)
UVM_INFO @ 10100096325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:
44.pattgen_inactive_level.8719533422459760049700140643213811986875302874369843438324275354712328480703
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/44.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10002765113 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xb512fd0, Comparison=CompareOpEq, exp_data=0x0, call_count=3)
UVM_INFO @ 10002765113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job returned non-zero exit code has 1 failures:
cov_merge
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/cov_merge/merged/cov_merge.log
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk cov_merge cov_merge_cmd=imc cov_merge_opts='-64bit -licqueue -exec /nightly/current_run/opentitan/hw/dv/tools/xcelium/cov_merge.tcl'
[make]: cov_merge
imc -64bit -licqueue -exec /nightly/current_run/opentitan/hw/dv/tools/xcelium/cov_merge.tcl
*I,imc.tool.cov.version.diff: "There is a difference between the IMC tool version 22.09 and the coverage version 21.09-s006"
Error: Cannot invoke "jdk.internal.platform.CgroupInfo.getMountPoint()" because "<parameter1>" is null
Created log file /nightly/current_run/opentitan/startup.log
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:231: cov_merge] Error 1
Job killed most likely because its dependent job failed. has 1 failures: