RV_TIMER Simulation Results

Tuesday September 09 2025 00:00:40 UTC

GitHub Revision: 2144e83

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 random rv_timer_random 3.000s 6.874us 0 20 0.00
V1 csr_hw_reset rv_timer_csr_hw_reset 3.000s 19.922us 5 5 100.00
V1 csr_rw rv_timer_csr_rw 3.000s 12.826us 20 20 100.00
V1 csr_bit_bash rv_timer_csr_bit_bash 4.000s 66.367us 5 5 100.00
V1 csr_aliasing rv_timer_csr_aliasing 3.000s 158.959us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rv_timer_csr_mem_rw_with_rand_reset 3.000s 47.985us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rv_timer_csr_rw 3.000s 12.826us 20 20 100.00
rv_timer_csr_aliasing 3.000s 158.959us 5 5 100.00
V1 TOTAL 55 75 73.33
V2 random_reset rv_timer_random_reset 8.000s 59.523us 0 20 0.00
V2 disabled rv_timer_disabled 6.000s 3.308ms 20 20 100.00
V2 cfg_update_on_fly rv_timer_cfg_update_on_fly 9.283m 879.027ms 10 10 100.00
V2 no_interrupt_test rv_timer_cfg_update_on_fly 9.283m 879.027ms 10 10 100.00
V2 stress rv_timer_stress_all 13.000s 8.597ms 5 20 25.00
V2 alert_test rv_timer_alert_test 3.000s 11.006us 50 50 100.00
V2 intr_test rv_timer_intr_test 3.000s 11.073us 50 50 100.00
V2 tl_d_oob_addr_access rv_timer_tl_errors 5.000s 382.191us 20 20 100.00
V2 tl_d_illegal_access rv_timer_tl_errors 5.000s 382.191us 20 20 100.00
V2 tl_d_outstanding_access rv_timer_csr_hw_reset 3.000s 19.922us 5 5 100.00
rv_timer_csr_rw 3.000s 12.826us 20 20 100.00
rv_timer_csr_aliasing 3.000s 158.959us 5 5 100.00
rv_timer_same_csr_outstanding 3.000s 11.473us 20 20 100.00
V2 tl_d_partial_access rv_timer_csr_hw_reset 3.000s 19.922us 5 5 100.00
rv_timer_csr_rw 3.000s 12.826us 20 20 100.00
rv_timer_csr_aliasing 3.000s 158.959us 5 5 100.00
rv_timer_same_csr_outstanding 3.000s 11.473us 20 20 100.00
V2 TOTAL 175 210 83.33
V2S tl_intg_err rv_timer_sec_cm 3.000s 126.579us 5 5 100.00
rv_timer_tl_intg_err 4.000s 387.749us 20 20 100.00
V2S sec_cm_bus_integrity rv_timer_tl_intg_err 4.000s 387.749us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 min_value rv_timer_min 3.000s 1.458us 0 10 0.00
V3 max_value rv_timer_max 3.000s 2.136us 0 10 0.00
V3 stress_all_with_rand_reset rv_timer_stress_all_with_rand_reset 17.000s 1.640ms 0 20 0.00
V3 TOTAL 0 40 0.00
TOTAL 255 350 72.86

Failure Buckets