2144e83| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | sysrst_ctrl_smoke | 15.000s | 2.112ms | 50 | 50 | 100.00 |
| V1 | input_output_inverted | sysrst_ctrl_in_out_inverted | 18.000s | 2.489ms | 50 | 50 | 100.00 |
| V1 | combo_detect_ec_rst | sysrst_ctrl_combo_detect_ec_rst | 15.000s | 2.193ms | 5 | 5 | 100.00 |
| V1 | combo_detect_ec_rst_with_pre_cond | sysrst_ctrl_combo_detect_ec_rst_with_pre_cond | 16.000s | 2.544ms | 5 | 5 | 100.00 |
| V1 | csr_hw_reset | sysrst_ctrl_csr_hw_reset | 35.000s | 6.015ms | 5 | 5 | 100.00 |
| V1 | csr_rw | sysrst_ctrl_csr_rw | 14.000s | 2.032ms | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | sysrst_ctrl_csr_bit_bash | 1.683m | 39.164ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | sysrst_ctrl_csr_aliasing | 11.000s | 2.475ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | sysrst_ctrl_csr_mem_rw_with_rand_reset | 15.000s | 2.081ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | sysrst_ctrl_csr_rw | 14.000s | 2.032ms | 20 | 20 | 100.00 |
| sysrst_ctrl_csr_aliasing | 11.000s | 2.475ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 165 | 165 | 100.00 | |||
| V2 | combo_detect | sysrst_ctrl_combo_detect | 17.267m | 218.893ms | 50 | 50 | 100.00 |
| V2 | combo_detect_with_pre_cond | sysrst_ctrl_combo_detect_with_pre_cond | 20.700m | 265.469ms | 95 | 100 | 95.00 |
| V2 | auto_block_key_outputs | sysrst_ctrl_auto_blk_key_output | 17.150m | 232.039ms | 49 | 50 | 98.00 |
| V2 | keyboard_input_triggered_interrupt | sysrst_ctrl_edge_detect | 26.000s | 5.021ms | 45 | 50 | 90.00 |
| V2 | pin_output_keyboard_inversion_control | sysrst_ctrl_pin_override_test | 17.000s | 2.510ms | 50 | 50 | 100.00 |
| V2 | pin_input_value_accessibility | sysrst_ctrl_pin_access_test | 14.000s | 2.150ms | 50 | 50 | 100.00 |
| V2 | ec_power_on_reset | sysrst_ctrl_ec_pwr_on_rst | 46.350m | 805.429ms | 48 | 50 | 96.00 |
| V2 | flash_write_protect_output | sysrst_ctrl_flash_wr_prot_out | 18.000s | 2.612ms | 50 | 50 | 100.00 |
| V2 | ultra_low_power_test | sysrst_ctrl_ultra_low_pwr | 8.950m | 3.755s | 39 | 50 | 78.00 |
| V2 | sysrst_ctrl_feature_disable | sysrst_ctrl_feature_disable | 1.867m | 31.369ms | 2 | 2 | 100.00 |
| V2 | stress_all | sysrst_ctrl_stress_all | 54.200m | 768.833ms | 47 | 50 | 94.00 |
| V2 | alert_test | sysrst_ctrl_alert_test | 14.000s | 2.012ms | 50 | 50 | 100.00 |
| V2 | intr_test | sysrst_ctrl_intr_test | 14.000s | 2.014ms | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | sysrst_ctrl_tl_errors | 15.000s | 2.078ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | sysrst_ctrl_tl_errors | 15.000s | 2.078ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | sysrst_ctrl_csr_hw_reset | 35.000s | 6.015ms | 5 | 5 | 100.00 |
| sysrst_ctrl_csr_rw | 14.000s | 2.032ms | 20 | 20 | 100.00 | ||
| sysrst_ctrl_csr_aliasing | 11.000s | 2.475ms | 5 | 5 | 100.00 | ||
| sysrst_ctrl_same_csr_outstanding | 35.000s | 7.988ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | sysrst_ctrl_csr_hw_reset | 35.000s | 6.015ms | 5 | 5 | 100.00 |
| sysrst_ctrl_csr_rw | 14.000s | 2.032ms | 20 | 20 | 100.00 | ||
| sysrst_ctrl_csr_aliasing | 11.000s | 2.475ms | 5 | 5 | 100.00 | ||
| sysrst_ctrl_same_csr_outstanding | 35.000s | 7.988ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 665 | 692 | 96.10 | |||
| V2S | tl_intg_err | sysrst_ctrl_sec_cm | 3.600m | 42.012ms | 5 | 5 | 100.00 |
| sysrst_ctrl_tl_intg_err | 3.317m | 42.407ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | sysrst_ctrl_tl_intg_err | 3.317m | 42.407ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | sysrst_ctrl_stress_all_with_rand_reset | 40.000s | 7.392ms | 36 | 50 | 72.00 |
| V3 | TOTAL | 36 | 50 | 72.00 | |||
| TOTAL | 891 | 932 | 95.60 |
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 10 failures:
Test sysrst_ctrl_stress_all has 2 failures.
4.sysrst_ctrl_stress_all.37772375966436334628467825266577029428528429328043480254539803929373902584417
Line 400, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-xcelium/4.sysrst_ctrl_stress_all/latest/run.log
UVM_ERROR @ 5173062454 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_ERROR @ 5173098168 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 5173098168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.sysrst_ctrl_stress_all.71683392764615232766501642695019255875000545212858271146999864863915012591842
Line 434, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-xcelium/11.sysrst_ctrl_stress_all/latest/run.log
UVM_ERROR @ 118963933371 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_ERROR @ 118963963370 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 118963963370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test sysrst_ctrl_ultra_low_pwr has 4 failures.
8.sysrst_ctrl_ultra_low_pwr.23746971923642533820497719481780374442655569258832359184538009160404677023936
Line 390, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-xcelium/8.sysrst_ctrl_ultra_low_pwr/latest/run.log
UVM_ERROR @ 2760162007 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_ERROR @ 2760222006 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 2760222006 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
14.sysrst_ctrl_ultra_low_pwr.106745881326237578055339624727747625585398030451378060097136847107539152941548
Line 391, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-xcelium/14.sysrst_ctrl_ultra_low_pwr/latest/run.log
UVM_ERROR @ 3993694970 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_ERROR @ 3993724969 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 3993724969 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Test sysrst_ctrl_edge_detect has 4 failures.
10.sysrst_ctrl_edge_detect.40428815590443544375815812997052324790121617355447453895734259352944605669903
Line 406, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-xcelium/10.sysrst_ctrl_edge_detect/latest/run.log
UVM_ERROR @ 3112603310 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_ERROR @ 3112674739 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 3112674739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.sysrst_ctrl_edge_detect.54913954417812413179340949780169344202557607829129710094766891602179688852625
Line 399, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-xcelium/13.sysrst_ctrl_edge_detect/latest/run.log
UVM_ERROR @ 2669743255 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_ERROR @ 2669863254 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 2669863254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) has 7 failures:
0.sysrst_ctrl_ultra_low_pwr.88680825813552151541275055445006471820075322835785325761446592354708219869617
Line 391, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-xcelium/0.sysrst_ctrl_ultra_low_pwr/latest/run.log
UVM_ERROR @ 2752329891 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)
UVM_INFO @ 2754829891 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i
UVM_INFO @ 3224829891 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
UVM_INFO @ 3243212631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.sysrst_ctrl_ultra_low_pwr.38269732492617891032659245636789219752621604012724253639723017183439883512409
Line 390, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-xcelium/11.sysrst_ctrl_ultra_low_pwr/latest/run.log
UVM_ERROR @ 2181079463 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)
UVM_INFO @ 2198579463 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i
UVM_INFO @ 2548579463 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
UVM_INFO @ 2593207288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
xmsim: *E,COVITS: Covergroup instance sysrst_ctrl_key_invert_ctl_cg (/nightly/current_run/scratch/master/sysrst_ctrl-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_sysrst_ctrl_env_*/seq_lib/sysrst_ctrl_in_out_inverted_vseq.sv:19) with 'sysrst_ctrl_key_invert_ctl_cg' as the instance name will not be saved to the database and its coverage will be merged with another covergroup instance sysrst_ctrl_key_invert_ctl_cg (/nightly/current_run/scratch/master/sysrst_ctrl-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_sysrst_ctrl_env_*/seq_lib/sysrst_ctrl_in_out_inverted_vseq.sv:19) with the same instance name 'sysrst_ctrl_key_invert_ctl_cg'. This is because both the covergroup instances are having same description and are defined in the same scope with the same name. has 7 failures:
0.sysrst_ctrl_stress_all_with_rand_reset.11777900263093270321679141440460373232925087429509635063273155020046597740906
Line 519, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-xcelium/0.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
xmsim: *E,COVITS: Covergroup instance sysrst_ctrl_key_invert_ctl_cg (/nightly/current_run/scratch/master/sysrst_ctrl-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_sysrst_ctrl_env_0.1/seq_lib/sysrst_ctrl_in_out_inverted_vseq.sv:19) with 'sysrst_ctrl_key_invert_ctl_cg' as the instance name will not be saved to the database and its coverage will be merged with another covergroup instance sysrst_ctrl_key_invert_ctl_cg (/nightly/current_run/scratch/master/sysrst_ctrl-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_sysrst_ctrl_env_0.1/seq_lib/sysrst_ctrl_in_out_inverted_vseq.sv:19) with the same instance name 'sysrst_ctrl_key_invert_ctl_cg'. This is because both the covergroup instances are having same description and are defined in the same scope with the same name.
xmsim: *W,COVNBT: (/nightly/current_run/scratch/master/sysrst_ctrl-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:281): Name of named block scope "gen_h2d" shall not be suffixed with a redundant "_T" in IMC type-based coverage in subsequent release in default mode. There may be other such named block scopes in the design.
xmsim: *W,CGNSIN: Name of covergroup instance "sysrst_ctrl_auto_block_debounce_ctl_cg" is same as the name of the covergroup "sysrst_ctrl_auto_block_debounce_ctl_cg".
xmsim: *W,CGNSIN: Name of covergroup instance "sysrst_ctrl_key_intr_status_cg" is same as the name of the covergroup "sysrst_ctrl_key_intr_status_cg".
xmsim: *W,CGNSIN: Name of covergroup instance "sysrst_ctrl_pin_in_value_cg" is same as the name of the covergroup "sysrst_ctrl_pin_in_value_cg".
1.sysrst_ctrl_stress_all_with_rand_reset.23234605383434489320738745742705198585890868588420055537484140008349944713012
Line 522, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-xcelium/1.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
xmsim: *E,COVITS: Covergroup instance sysrst_ctrl_key_invert_ctl_cg (/nightly/current_run/scratch/master/sysrst_ctrl-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_sysrst_ctrl_env_0.1/seq_lib/sysrst_ctrl_in_out_inverted_vseq.sv:19) with 'sysrst_ctrl_key_invert_ctl_cg' as the instance name will not be saved to the database and its coverage will be merged with another covergroup instance sysrst_ctrl_key_invert_ctl_cg (/nightly/current_run/scratch/master/sysrst_ctrl-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_sysrst_ctrl_env_0.1/seq_lib/sysrst_ctrl_in_out_inverted_vseq.sv:19) with the same instance name 'sysrst_ctrl_key_invert_ctl_cg'. This is because both the covergroup instances are having same description and are defined in the same scope with the same name.
xmsim: *E,COVITS: Covergroup instance sysrst_ctrl_key_invert_ctl_cg (/nightly/current_run/scratch/master/sysrst_ctrl-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_sysrst_ctrl_env_0.1/seq_lib/sysrst_ctrl_in_out_inverted_vseq.sv:19) with 'sysrst_ctrl_key_invert_ctl_cg' as the instance name will not be saved to the database and its coverage will be merged with another covergroup instance sysrst_ctrl_key_invert_ctl_cg (/nightly/current_run/scratch/master/sysrst_ctrl-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_sysrst_ctrl_env_0.1/seq_lib/sysrst_ctrl_in_out_inverted_vseq.sv:19) with the same instance name 'sysrst_ctrl_key_invert_ctl_cg'. This is because both the covergroup instances are having same description and are defined in the same scope with the same name.
xmsim: *W,COVNBT: (/nightly/current_run/scratch/master/sysrst_ctrl-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:281): Name of named block scope "gen_h2d" shall not be suffixed with a redundant "_T" in IMC type-based coverage in subsequent release in default mode. There may be other such named block scopes in the design.
xmsim: *W,CGNSIN: Name of covergroup instance "sysrst_ctrl_auto_block_debounce_ctl_cg" is same as the name of the covergroup "sysrst_ctrl_auto_block_debounce_ctl_cg".
xmsim: *W,CGNSIN: Name of covergroup instance "sysrst_ctrl_key_intr_status_cg" is same as the name of the covergroup "sysrst_ctrl_key_intr_status_cg".
... and 5 more failures.
xmsim: *E,COVITS: Covergroup instance sysrst_ctrl_auto_blk_out_ctl_cg (/nightly/current_run/scratch/master/sysrst_ctrl-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_sysrst_ctrl_env_*/seq_lib/sysrst_ctrl_auto_blk_key_output_vseq.sv:41) with 'sysrst_ctrl_auto_blk_out_ctl_cg' as the instance name will not be saved to the database and its coverage will be merged with another covergroup instance sysrst_ctrl_auto_blk_out_ctl_cg (/nightly/current_run/scratch/master/sysrst_ctrl-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_sysrst_ctrl_env_*/seq_lib/sysrst_ctrl_auto_blk_key_output_vseq.sv:41) with the same instance name 'sysrst_ctrl_auto_blk_out_ctl_cg'. This is because both the covergroup instances are having same description and are defined in the same scope with the same name. has 7 failures:
3.sysrst_ctrl_stress_all_with_rand_reset.63354353777846042113505331540036267839015128232718946886010018796083729770481
Line 487, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-xcelium/3.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
xmsim: *E,COVITS: Covergroup instance sysrst_ctrl_auto_blk_out_ctl_cg (/nightly/current_run/scratch/master/sysrst_ctrl-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_sysrst_ctrl_env_0.1/seq_lib/sysrst_ctrl_auto_blk_key_output_vseq.sv:41) with 'sysrst_ctrl_auto_blk_out_ctl_cg' as the instance name will not be saved to the database and its coverage will be merged with another covergroup instance sysrst_ctrl_auto_blk_out_ctl_cg (/nightly/current_run/scratch/master/sysrst_ctrl-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_sysrst_ctrl_env_0.1/seq_lib/sysrst_ctrl_auto_blk_key_output_vseq.sv:41) with the same instance name 'sysrst_ctrl_auto_blk_out_ctl_cg'. This is because both the covergroup instances are having same description and are defined in the same scope with the same name.
xmsim: *W,COVNBT: (/nightly/current_run/scratch/master/sysrst_ctrl-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:281): Name of named block scope "gen_h2d" shall not be suffixed with a redundant "_T" in IMC type-based coverage in subsequent release in default mode. There may be other such named block scopes in the design.
xmsim: *W,CGNSIN: Name of covergroup instance "sysrst_ctrl_auto_block_debounce_ctl_cg" is same as the name of the covergroup "sysrst_ctrl_auto_block_debounce_ctl_cg".
xmsim: *W,CGNSIN: Name of covergroup instance "sysrst_ctrl_key_intr_status_cg" is same as the name of the covergroup "sysrst_ctrl_key_intr_status_cg".
xmsim: *W,CGNSIN: Name of covergroup instance "sysrst_ctrl_pin_in_value_cg" is same as the name of the covergroup "sysrst_ctrl_pin_in_value_cg".
6.sysrst_ctrl_stress_all_with_rand_reset.26089686994707725283814197392043978820685138778658150362446159399659615968894
Line 537, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-xcelium/6.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
xmsim: *E,COVITS: Covergroup instance sysrst_ctrl_auto_blk_out_ctl_cg (/nightly/current_run/scratch/master/sysrst_ctrl-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_sysrst_ctrl_env_0.1/seq_lib/sysrst_ctrl_auto_blk_key_output_vseq.sv:41) with 'sysrst_ctrl_auto_blk_out_ctl_cg' as the instance name will not be saved to the database and its coverage will be merged with another covergroup instance sysrst_ctrl_auto_blk_out_ctl_cg (/nightly/current_run/scratch/master/sysrst_ctrl-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_sysrst_ctrl_env_0.1/seq_lib/sysrst_ctrl_auto_blk_key_output_vseq.sv:41) with the same instance name 'sysrst_ctrl_auto_blk_out_ctl_cg'. This is because both the covergroup instances are having same description and are defined in the same scope with the same name.
xmsim: *W,COVNBT: (/nightly/current_run/scratch/master/sysrst_ctrl-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:281): Name of named block scope "gen_h2d" shall not be suffixed with a redundant "_T" in IMC type-based coverage in subsequent release in default mode. There may be other such named block scopes in the design.
xmsim: *W,CGNSIN: Name of covergroup instance "sysrst_ctrl_auto_block_debounce_ctl_cg" is same as the name of the covergroup "sysrst_ctrl_auto_block_debounce_ctl_cg".
xmsim: *W,CGNSIN: Name of covergroup instance "sysrst_ctrl_key_intr_status_cg" is same as the name of the covergroup "sysrst_ctrl_key_intr_status_cg".
xmsim: *W,CGNSIN: Name of covergroup instance "sysrst_ctrl_pin_in_value_cg" is same as the name of the covergroup "sysrst_ctrl_pin_in_value_cg".
... and 5 more failures.
Job timed out after * minutes has 1 failures:
6.sysrst_ctrl_ec_pwr_on_rst.3554216131251336759212518349274516364295749865032046073614574793134622112564
Log /nightly/current_run/scratch/master/sysrst_ctrl-sim-xcelium/6.sysrst_ctrl_ec_pwr_on_rst/latest/run.log
Job timed out after 60 minutes
UVM_ERROR (sysrst_ctrl_auto_blk_key_output_vseq.sv:119) [sysrst_ctrl_auto_blk_key_output_vseq] Check failed override_key1_out_value == cfg.vif.key1_out (* [*] vs * [*]) has 1 failures:
13.sysrst_ctrl_auto_blk_key_output.40090274464156645071816858367630022680348221500966311294916309124042175459843
Line 392, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-xcelium/13.sysrst_ctrl_auto_blk_key_output/latest/run.log
UVM_ERROR @ 2426338276 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:119) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Check failed override_key1_out_value == cfg.vif.key1_out (1 [0x1] vs 0 [0x0])
UVM_INFO @ 2526703697 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:88) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Debounce timer set for: 1c
UVM_INFO @ 2756338276 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:100) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Value of cycles:30
UVM_INFO @ 2876706497 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:88) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Debounce timer set for: f
UVM_INFO @ 3036338276 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:100) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Value of cycles:10
UVM_FATAL (sysrst_ctrl_base_vseq.sv:70) [sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == * has 1 failures:
17.sysrst_ctrl_ec_pwr_on_rst.110954214379738185551456588019251497543548983143683246404229004115824334948898
Line 390, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-xcelium/17.sysrst_ctrl_ec_pwr_on_rst/latest/run.log
UVM_FATAL @ 2216100260 ps: (sysrst_ctrl_base_vseq.sv:70) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == 0
UVM_INFO @ 2216100260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:268) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(7) vs exp(3) +/-* has 1 failures:
24.sysrst_ctrl_combo_detect_with_pre_cond.12687963458494083436354522728925655470165468584782555204826402868795190554942
Line 500, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-xcelium/24.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 131176121678 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(7) vs exp(3) +/-4
UVM_INFO @ 131186121678 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:152) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_h2l_expected == 0
UVM_INFO @ 131376121678 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
UVM_INFO @ 131396121678 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
UVM_INFO @ 141467415790 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x2a
UVM_FATAL (cip_base_vseq.sv:574) [sysrst_ctrl_ultra_low_pwr_vseq] timeout occurred! has 1 failures:
33.sysrst_ctrl_stress_all.93199517514695626470885627797476026517124210196424791971280145399555351735315
Line 393, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-xcelium/33.sysrst_ctrl_stress_all/latest/run.log
UVM_FATAL @ 664673524717 ps: (cip_base_vseq.sv:574) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] timeout occurred!
UVM_INFO @ 664673524717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:574) [sysrst_ctrl_edge_detect_vseq] timeout occurred! has 1 failures:
34.sysrst_ctrl_edge_detect.69955636721809176206145745610592283149825863976588523166192094161660011604737
Line 408, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-xcelium/34.sysrst_ctrl_edge_detect/latest/run.log
UVM_FATAL @ 15283037887 ps: (cip_base_vseq.sv:574) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] timeout occurred!
UVM_INFO @ 15283037887 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == * (* [*] vs * [*]) has 1 failures:
54.sysrst_ctrl_combo_detect_with_pre_cond.102743377370864145635851146641950122456279528502514260822861627415008876650242
Line 403, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-xcelium/54.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 20398483174 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
UVM_ERROR @ 20598543502 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:570) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed rdata == intr_actions (0 [0x0] vs 4 [0x4])
UVM_INFO @ 20598543502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == * (* [*] vs * [*]) has 1 failures:
69.sysrst_ctrl_combo_detect_with_pre_cond.51307810788295414917291480176146492590012895419694517347616425257439263190501
Line 455, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-xcelium/69.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 78129268193 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 78184268193 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
UVM_INFO @ 78204268193 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
UVM_INFO @ 88439584849 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x30
UVM_INFO @ 88439814012 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:240) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x2c
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:254) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(9) vs exp(4) +/-* has 1 failures:
87.sysrst_ctrl_combo_detect_with_pre_cond.58367861063282506327774506429993834783766277087255414864151536105312742726662
Line 403, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-xcelium/87.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 14985921864 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:254) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(9) vs exp(4) +/-4
UVM_ERROR @ 14985921864 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:282) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(9) vs exp(4) +/-4
UVM_INFO @ 14985921864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*]) has 1 failures:
97.sysrst_ctrl_combo_detect_with_pre_cond.98332501601422783339911519891013389428422849590638665779879585097859960520892
Line 419, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-xcelium/97.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 15793067215 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 15988067215 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
UVM_INFO @ 16008067215 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
UVM_INFO @ 26099749731 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x30
UVM_INFO @ 26099829731 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:240) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x12
Job returned non-zero exit code has 1 failures:
cov_merge
Log /nightly/current_run/scratch/master/sysrst_ctrl-sim-xcelium/cov_merge/merged/cov_merge.log
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk cov_merge cov_merge_cmd=imc cov_merge_opts='-64bit -licqueue -exec /nightly/current_run/opentitan/hw/dv/tools/xcelium/cov_merge.tcl'
[make]: cov_merge
imc -64bit -licqueue -exec /nightly/current_run/opentitan/hw/dv/tools/xcelium/cov_merge.tcl
*I,imc.tool.cov.version.diff: "There is a difference between the IMC tool version 22.09 and the coverage version 21.09-s006"
Error: Cannot invoke "jdk.internal.platform.CgroupInfo.getMountPoint()" because "<parameter1>" is null
Created log file /nightly/current_run/opentitan/startup.log
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:231: cov_merge] Error 1
Job killed most likely because its dependent job failed. has 1 failures: