CHIP Simulation Results

Tuesday September 09 2025 00:00:40 UTC

GitHub Revision: `2144e83`

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	16.367m	2.831ms	3	3	100.00
		chip_sw_example_rom	8.200m	2.452ms	3	3	100.00
		chip_sw_example_manufacturer	15.383m	3.083ms	3	3	100.00
		chip_sw_example_concurrency	17.233m	2.689ms	3	3	100.00
V1	csr_hw_reset	chip_csr_hw_reset	20.550m	8.183ms	5	5	100.00
V1	csr_rw	chip_csr_rw	35.350m	5.813ms	20	20	100.00
V1	csr_bit_bash	chip_csr_bit_bash	47.883m	8.407ms	5	5	100.00
V1	csr_aliasing	chip_csr_aliasing			0	5	0.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	46.600m	10.637ms	10	20	50.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing			0	5	0.00
		chip_csr_rw	35.350m	5.813ms	20	20	100.00
V1	xbar_smoke	xbar_smoke	43.000s	51.306us	0	100	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	35.417m	4.844ms	3	3	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	35.417m	4.844ms	3	3	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	35.417m	4.844ms	3	3	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	41.450m	4.659ms	5	5	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	41.450m	4.659ms	5	5	100.00
		chip_sw_uart_tx_rx_idx1	41.033m	4.832ms	5	5	100.00
		chip_sw_uart_tx_rx_idx2	41.500m	4.340ms	5	5	100.00
		chip_sw_uart_tx_rx_idx3	41.200m	4.440ms	5	5	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	1.717h	8.506ms	14	20	70.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	1.755h	8.338ms	4	5	80.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed			0	5	0.00
V1		TOTAL			93	220	42.27
V2	chip_pin_mux	chip_padctrl_attributes	25.083m	4.614ms	10	10	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	25.083m	4.614ms	10	10	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	19.167m	3.522ms	1	3	33.33
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	15.917m	3.394ms	3	3	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	18.167m	2.772ms	3	3	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	30.550m	4.412ms	3	5	60.00
		chip_tap_straps_testunlock0	51.033m	5.173ms	4	5	80.00
		chip_tap_straps_rma	56.433m	6.623ms	5	5	100.00
		chip_tap_straps_prod	1.672h	9.115ms	4	5	80.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	17.567m	2.691ms	3	3	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses			0	3	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	49.683m	6.312ms	6	6	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	49.683m	6.312ms	6	6	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	58.200m	8.521ms	2	3	66.67
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs			0	3	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	35.833m	3.823ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	56.017m	5.668ms	1	3	33.33
		chip_sw_otbn_ecdsa_op_irq_jitter_en	5.031h	19.766ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	17.250m	2.707ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	56.567m	5.674ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	19.467m	3.545ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	1.071h	5.909ms	2	3	66.67
		chip_sw_kmac_mode_kmac_jitter_en	16.117m	3.551ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	31.317m	4.860ms	3	3	100.00
		chip_sw_clkmgr_jitter	12.483m	3.184ms	3	3	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	18.700m	3.191ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	55.417m	7.822ms	3	5	60.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	32.050m	5.905ms	3	3	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	15.700m	2.665ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	32.050m	5.905ms	3	3	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	17.367m	2.983ms	3	3	100.00
		chip_sw_aes_smoketest	15.850m	2.786ms	3	3	100.00
		chip_sw_aon_timer_smoketest	19.183m	3.050ms	3	3	100.00
		chip_sw_clkmgr_smoketest	14.250m	2.942ms	3	3	100.00
		chip_sw_csrng_smoketest	16.467m	2.295ms	3	3	100.00
		chip_sw_entropy_src_smoketest			0	3	0.00
		chip_sw_gpio_smoketest	18.767m	3.345ms	3	3	100.00
		chip_sw_hmac_smoketest	23.333m	3.828ms	3	3	100.00
		chip_sw_kmac_smoketest	19.367m	3.408ms	3	3	100.00
		chip_sw_otbn_smoketest	56.967m	5.402ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	26.233m	5.609ms	3	3	100.00
		chip_sw_pwrmgr_usbdev_smoketest	32.750m	5.781ms	3	3	100.00
		chip_sw_rv_plic_smoketest	16.933m	2.790ms	3	3	100.00
		chip_sw_rv_timer_smoketest	13.917m	3.210ms	3	3	100.00
		chip_sw_rstmgr_smoketest	15.183m	3.046ms	3	3	100.00
		chip_sw_sram_ctrl_smoketest	17.517m	2.436ms	3	3	100.00
		chip_sw_uart_smoketest	17.067m	3.230ms	3	3	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	16.200m	2.967ms	3	3	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	37.133m	5.230ms	3	3	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap			0	3	0.00
V2	chip_sw_secure_boot	rom_e2e_smoke			0	3	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	1.337h	16.610ms	2	3	66.67
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	21.900m	3.659ms	0	3	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	24.217m	4.080ms	0	3	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap			0	3	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed			0	3	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	19.950m	5.053ms	8	30	26.67
V2	tl_d_illegal_access	chip_tl_errors	19.950m	5.053ms	8	30	26.67
V2	tl_d_outstanding_access	chip_csr_aliasing			0	5	0.00
		chip_same_csr_outstanding	1.969h	15.597ms	3	20	15.00
		chip_csr_hw_reset	20.550m	8.183ms	5	5	100.00
		chip_csr_rw	35.350m	5.813ms	20	20	100.00
V2	tl_d_partial_access	chip_csr_aliasing			0	5	0.00
		chip_same_csr_outstanding	1.969h	15.597ms	3	20	15.00
		chip_csr_hw_reset	20.550m	8.183ms	5	5	100.00
		chip_csr_rw	35.350m	5.813ms	20	20	100.00
V2	xbar_base_random_sequence	xbar_random	2.350m	2.463ms	0	100	0.00
V2	xbar_random_delay	xbar_smoke_zero_delays	57.000s	42.573us	0	100	0.00
		xbar_smoke_large_delays	2.383m	10.629ms	0	100	0.00
		xbar_smoke_slow_rsp	2.317m	6.666ms	0	100	0.00
		xbar_random_zero_delays	1.533m	628.136us	0	100	0.00
		xbar_random_large_delays	11.200m	61.443ms	0	100	0.00
		xbar_random_slow_rsp	9.783m	36.177ms	0	100	0.00
V2	xbar_unmapped_address	xbar_unmapped_addr	1.617m	1.437ms	0	100	0.00
		xbar_error_and_unmapped_addr	1.550m	1.373ms	0	100	0.00
V2	xbar_error_cases	xbar_error_random	2.233m	2.668ms	0	100	0.00
		xbar_error_and_unmapped_addr	1.550m	1.373ms	0	100	0.00
V2	xbar_all_access_same_device	xbar_access_same_device	3.417m	3.699ms	0	100	0.00
		xbar_access_same_device_slow_rsp	22.050m	76.061ms	0	100	0.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	2.417m	2.636ms	0	100	0.00
V2	xbar_stress_all	xbar_stress_all	15.883m	18.099ms	0	100	0.00
		xbar_stress_all_with_error	16.400m	18.859ms	0	100	0.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	22.083m	8.160ms	0	100	0.00
		xbar_stress_all_with_reset_error	26.383m	28.736ms	0	100	0.00
V2	rom_e2e_smoke	rom_e2e_smoke			0	3	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	1.113h	9.982ms	0	3	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	3.906h	14.796ms	0	3	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	3.160h	10.816ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	4.517h	14.979ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	4.521h	15.807ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	4.576h	15.766ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	25.000s	10.260us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	26.000s	10.280us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	26.000s	10.100us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	26.000s	10.100us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	27.000s	10.180us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	25.000s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	27.000s	10.260us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	26.000s	10.200us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	27.000s	10.100us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	26.000s	10.200us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	25.000s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	24.000s	10.320us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	26.000s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	24.000s	10.320us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	26.000s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	24.000s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	24.000s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	26.000s	10.320us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	26.000s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	25.000s	10.320us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	23.000s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	28.000s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	26.000s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	25.000s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	27.000s	10.380us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	3.281h	12.442ms	3	3	100.00
		rom_e2e_asm_init_dev	4.557h	15.611ms	2	3	66.67
		rom_e2e_asm_init_prod	4.613h	15.958ms	2	3	66.67
		rom_e2e_asm_init_prod_end	4.577h	14.950ms	2	3	66.67
		rom_e2e_asm_init_rma	4.464h	15.179ms	3	3	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas			0	3	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas			0	3	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas			0	3	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical			0	3	0.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup			0	3	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup			0	3	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	15.450m	3.367ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	17.250m	2.707ms	3	3	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	17.033m	3.563ms	3	3	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	16.433m	2.410ms	3	3	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes			0	3	0.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	16.767m	2.925ms	0	3	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	37.200m	5.209ms	3	3	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	48.950m	6.056ms	95	100	95.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	58.650m	5.546ms	1	3	33.33
		chip_plic_all_irqs_10	30.717m	3.467ms	3	3	100.00
		chip_plic_all_irqs_20	42.017m	4.891ms	3	3	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	22.933m	3.228ms	3	3	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	1.897h	11.713ms	2	3	66.67
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	48.467m	5.585ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	17.400m	2.892ms	0	90	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	1.336h	11.174ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	2.322h	9.207ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	2.201h	9.304ms	3	3	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok			0	3	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep			0	3	0.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	33.600m	4.592ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	26.233m	5.609ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	33.600m	4.592ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	55.283m	7.921ms	2	3	66.67
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	55.283m	7.921ms	2	3	66.67
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	31.733m	7.646ms	5	5	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	45.983m	4.516ms	3	3	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness			0	3	0.00
		chip_sw_aes_idle	16.433m	2.410ms	3	3	100.00
		chip_sw_hmac_enc_idle	20.150m	3.305ms	3	3	100.00
		chip_sw_kmac_idle	15.583m	2.824ms	3	3	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	31.150m	4.103ms	3	3	100.00
		chip_sw_clkmgr_off_hmac_trans	26.583m	4.529ms	3	3	100.00
		chip_sw_clkmgr_off_kmac_trans	30.500m	4.483ms	3	3	100.00
		chip_sw_clkmgr_off_otbn_trans	34.967m	5.431ms	3	3	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri			0	3	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	36.883m	4.008ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	39.650m	4.510ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	38.150m	3.741ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	38.200m	4.627ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	38.017m	4.202ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	42.267m	4.776ms	3	3	100.00
		chip_sw_ast_clk_outputs	58.200m	8.521ms	2	3	66.67
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	39.900m	6.242ms	2	3	66.67
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	38.150m	3.741ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	38.200m	4.627ms	3	3	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	35.833m	3.823ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	56.017m	5.668ms	1	3	33.33
		chip_sw_otbn_ecdsa_op_irq_jitter_en	5.031h	19.766ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	17.250m	2.707ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	56.567m	5.674ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	19.467m	3.545ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	1.071h	5.909ms	2	3	66.67
		chip_sw_kmac_mode_kmac_jitter_en	16.117m	3.551ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	31.317m	4.860ms	3	3	100.00
		chip_sw_clkmgr_jitter	12.483m	3.184ms	3	3	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	14.567m	3.436ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	36.150m	4.374ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq			0	3	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	5.149h	24.980ms	3	3	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	14.200m	2.915ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	15.133m	3.025ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq			0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	18.117m	3.341ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	32.033m	5.164ms	3	3	100.00
		chip_sw_flash_init_reduced_freq			0	3	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	2.759h	13.299ms	1	3	33.33
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	58.200m	8.521ms	2	3	66.67
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	36.517m	4.205ms	3	3	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	27.167m	3.770ms	3	3	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	48.950m	6.056ms	95	100	95.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	2.322h	9.207ms	3	3	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	1.749h	8.070ms	3	3	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	28.833m	4.086ms	3	3	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	53.217m	7.257ms	3	3	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	13.417m	2.964ms	3	3	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	3.777h	17.455ms	4	10	40.00
		chip_sw_entropy_src_ast_rng_req	16.933m	3.148ms	3	3	100.00
		chip_sw_edn_entropy_reqs			0	3	0.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	16.933m	3.148ms	3	3	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	1.749h	8.070ms	3	3	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	14.883m	2.852ms	3	3	100.00
V2	chip_sw_flash_init	chip_sw_flash_init			0	3	0.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	58.817m	6.043ms	1	3	33.33
		chip_sw_flash_ctrl_access_jitter_en	56.017m	5.668ms	1	3	33.33
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	34.917m	4.020ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en	35.833m	3.823ms	3	3	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked			0	3	0.00
V2	chip_sw_flash_scramble	chip_sw_flash_init			0	3	0.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	23.600m	3.784ms	3	3	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation			0	3	0.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	35.000m	5.563ms	3	3	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked			0	3	0.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	35.000m	5.563ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	35.000m	5.563ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	35.000m	5.563ms	3	3	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	35.000m	5.563ms	3	3	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	48.950m	6.056ms	95	100	95.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	21.667m	9.026ms	3	3	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	56.933m	5.230ms	3	3	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	45.233m	5.218ms	3	3	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	45.233m	5.218ms	3	3	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	18.783m	2.896ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	19.467m	3.545ms	3	3	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	20.150m	3.305ms	3	3	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	18.283m	3.005ms	0	3	0.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	31.150m	3.913ms	3	3	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	53.417m	5.063ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx1	51.433m	4.892ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx2	52.183m	5.367ms	3	3	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	39.750m	4.249ms	3	3	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation			0	3	0.00
		chip_sw_keymgr_key_derivation_jitter_en	1.071h	5.909ms	2	3	66.67
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac			0	3	0.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes			0	3	0.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	2.848h	10.571ms	1	3	33.33
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	17.333m	2.729ms	3	3	100.00
		chip_sw_kmac_mode_kmac	18.967m	3.166ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	16.117m	3.551ms	3	3	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation			0	3	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	49.950m	10.110ms	10	15	66.67
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	15.650m	2.708ms	3	3	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy			0	3	0.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	15.583m	2.824ms	3	3	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	37.200m	5.209ms	3	3	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	30.550m	4.412ms	3	5	60.00
		chip_tap_straps_rma	56.433m	6.623ms	5	5	100.00
		chip_tap_straps_prod	1.672h	9.115ms	4	5	80.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	18.233m	2.907ms	3	3	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	49.950m	10.110ms	10	15	66.67
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	49.950m	10.110ms	10	15	66.67
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	49.950m	10.110ms	10	15	66.67
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod			0	3	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	35.000m	5.563ms	3	3	100.00
		chip_sw_flash_rma_unlocked			0	3	0.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	25.367m	3.752ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev			0	3	0.00
		chip_sw_otp_ctrl_lc_signals_prod	59.217m	7.785ms	2	3	66.67
		chip_sw_otp_ctrl_lc_signals_rma	54.483m	6.548ms	1	3	33.33
		chip_sw_lc_ctrl_transition	49.950m	10.110ms	10	15	66.67
		chip_sw_keymgr_key_derivation			0	3	0.00
		chip_sw_rom_ctrl_integrity_check	52.133m	8.498ms	3	3	100.00
		chip_sw_sram_ctrl_execution_main	59.017m	8.755ms	1	3	33.33
		chip_prim_tl_access	21.667m	9.026ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	39.900m	6.242ms	2	3	66.67
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	36.883m	4.008ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	39.650m	4.510ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	38.150m	3.741ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	38.200m	4.627ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	38.017m	4.202ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	42.267m	4.776ms	3	3	100.00
		chip_tap_straps_dev	30.550m	4.412ms	3	5	60.00
		chip_tap_straps_rma	56.433m	6.623ms	5	5	100.00
		chip_tap_straps_prod	1.672h	9.115ms	4	5	80.00
		chip_rv_dm_lc_disabled	39.983m	14.870ms	3	3	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	14.750m	3.531ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	9.283m	3.294ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	8.633m	2.867ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	18.167m	3.296ms	2	3	66.67
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks			0	3	0.00
		chip_rv_dm_lc_disabled	39.983m	14.870ms	3	3	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev			0	3	0.00
		chip_sw_lc_walkthrough_prod			0	3	0.00
		chip_sw_lc_walkthrough_prodend	57.600m	7.250ms	1	3	33.33
		chip_sw_lc_walkthrough_rma			0	3	0.00
		chip_sw_lc_walkthrough_testunlocks			0	3	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	8.417m	2.507ms	3	3	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	7.667m	2.877ms	3	3	100.00
		rom_volatile_raw_unlock	7.150m	2.634ms	3	3	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	4.766h	16.507ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	5.031h	19.766ms	3	3	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness			0	3	0.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness			0	3	0.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness			0	3	0.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	32.883m	3.938ms	3	3	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	49.950m	10.110ms	10	15	66.67
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init			0	3	0.00
		chip_sw_otbn_mem_scramble	32.883m	3.938ms	3	3	100.00
		chip_sw_keymgr_key_derivation			0	3	0.00
		chip_sw_sram_ctrl_scrambled_access	32.283m	4.498ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	19.550m	3.457ms	3	3	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init			0	3	0.00
		chip_sw_otbn_mem_scramble	32.883m	3.938ms	3	3	100.00
		chip_sw_keymgr_key_derivation			0	3	0.00
		chip_sw_sram_ctrl_scrambled_access	32.283m	4.498ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	19.550m	3.457ms	3	3	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	49.950m	10.110ms	10	15	66.67
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	37.167m	4.541ms	3	3	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	18.233m	2.907ms	3	3	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	25.367m	3.752ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev			0	3	0.00
		chip_sw_otp_ctrl_lc_signals_prod	59.217m	7.785ms	2	3	66.67
		chip_sw_otp_ctrl_lc_signals_rma	54.483m	6.548ms	1	3	33.33
		chip_sw_lc_ctrl_transition	49.950m	10.110ms	10	15	66.67
		chip_prim_tl_access	21.667m	9.026ms	3	3	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	21.667m	9.026ms	3	3	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	1.928h	8.282ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	36.367m	7.327ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups			0	3	0.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	24.167m	6.845ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	45.433m	6.650ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	46.083m	6.136ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups			0	3	0.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	1.751h	13.947ms	3	3	100.00
		chip_sw_aon_timer_wdog_bite_reset	55.283m	7.921ms	2	3	66.67
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	1.667h	10.626ms	3	3	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	41.933m	4.785ms	3	3	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	36.367m	7.327ms	3	3	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	16.133m	3.552ms	0	3	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	1.616h	12.652ms	0	3	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	15.817m	3.092ms	0	3	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	15.650m	2.724ms	0	3	0.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs			0	3	0.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset			0	3	0.00
		chip_sw_pwrmgr_all_reset_reqs	1.830h	11.223ms	3	3	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req			0	3	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	17.850m	3.508ms	3	3	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	48.950m	6.056ms	95	100	95.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	52.133m	8.498ms	3	3	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	52.133m	8.498ms	3	3	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	1.830h	11.223ms	3	3	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs			0	3	0.00
		chip_sw_pwrmgr_wdog_reset	41.933m	4.785ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	26.233m	5.609ms	3	3	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	31.267m	4.248ms	3	3	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	28.150m	4.442ms	0	3	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	26.967m	4.343ms	3	3	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	1.897h	11.713ms	2	3	66.67
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	15.283m	2.924ms	3	3	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	48.950m	6.056ms	95	100	95.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	2.201h	9.304ms	3	3	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	49.550m	4.875ms	3	3	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	50.583m	4.591ms	3	3	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	16.200m	2.867ms	3	3	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	19.550m	3.457ms	3	3	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	28.150m	4.442ms	0	3	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	28.150m	4.442ms	0	3	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw			0	3	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access			0	3	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	31.267m	4.248ms	3	3	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	35.300m	4.496ms	3	3	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	30.700m	6.202ms	3	3	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	56.433m	6.623ms	5	5	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	39.983m	14.870ms	3	3	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	58.650m	5.546ms	1	3	33.33
		chip_plic_all_irqs_10	30.717m	3.467ms	3	3	100.00
		chip_plic_all_irqs_20	42.017m	4.891ms	3	3	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	15.867m	2.228ms	3	3	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	19.200m	3.421ms	3	3	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke			0	3	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through			0	3	0.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	23.600m	2.981ms	0	3	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	22.967m	3.571ms	3	3	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	18.800m	3.034ms	3	3	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	32.283m	4.498ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	31.317m	4.860ms	3	3	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	49.283m	7.801ms	3	3	100.00
		chip_sw_sleep_sram_ret_contents_scramble	51.100m	7.921ms	3	3	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	59.017m	8.755ms	1	3	33.33
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	48.950m	6.056ms	95	100	95.00
		chip_sw_data_integrity_escalation	49.683m	6.312ms	6	6	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset			0	3	0.00
		chip_sw_sysrst_ctrl_reset			0	3	0.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	16.750m	3.026ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	27.000m	4.119ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	40.650m	4.417ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset			0	3	0.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset			0	3	0.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	2.030h	11.110ms	0	3	0.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	2.030h	11.110ms	0	3	0.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	35.267m	6.306ms	3	3	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup			0	3	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	11.883m	2.892ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	16.300m	2.657ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	29.750m	3.482ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	37.017m	3.982ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host			0	1	0.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg			0	1	0.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi			0	1	0.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	18.567m	3.454ms	1	1	100.00
V2		TOTAL			586	2657	22.05
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	17.717m	3.021ms	3	3	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	8.017m	2.612ms	2	3	66.67
V2S		TOTAL			5	6	83.33
V3	chip_sw_coremark	chip_sw_coremark			0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	42.833m	3.486ms	0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	2.464h	12.368ms	1	1	100.00
		rom_e2e_jtag_debug_dev	17.117m	3.912ms	0	1	0.00
		rom_e2e_jtag_debug_rma	2.147h	10.173ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	22.917m	4.774ms	1	1	100.00
		rom_e2e_jtag_inject_dev	23.367m	5.155ms	1	1	100.00
		rom_e2e_jtag_inject_rma	23.667m	5.369ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	17.595s		0	3	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	54.283m	5.567ms	3	3	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	31.117m	2.818ms	3	3	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	1.204h	5.138ms	2	3	66.67
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode			0	3	0.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	22.517m	2.541ms	3	3	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	59.467m	5.274ms	3	3	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	7.117m	2.926ms	3	3	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	49.917m	4.950ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	30.300m	6.517ms	2	3	66.67
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	36.650m	4.441ms	3	3	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	1.830h	11.223ms	3	3	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	2.464h	12.368ms	1	1	100.00
		rom_e2e_jtag_debug_dev	17.117m	3.912ms	0	1	0.00
		rom_e2e_jtag_debug_rma	2.147h	10.173ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	43.817m	4.710ms	3	3	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	48.950m	6.056ms	95	100	95.00
V3	tick_configuration	chip_sw_rv_timer_systick_test			0	3	0.00
V3	counter_wrap	chip_sw_rv_timer_systick_test			0	3	0.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	15.750m	3.338ms	3	3	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	41.450m	4.659ms	5	5	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream			0	1	0.00
V3		TOTAL			34	51	66.67
	Unmapped tests	chip_sival_flash_info_access	17.500m	2.737ms	3	3	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	45.033m	5.764ms	3	3	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	14.783m	2.745ms	3	3	100.00
		chip_sw_otp_ctrl_descrambling	18.750m	2.898ms	3	3	100.00
		chip_sw_pwrmgr_lowpower_cancel	28.667m	3.856ms	3	3	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	14.991s		0	3	0.00
		chip_sw_flash_ctrl_write_clear	20.767m	3.008ms	3	3	100.00
		TOTAL			736	2955	24.91

Failure Buckets

xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_*/xbar_env_cov.sv:25) with 'rv_core_ibex__cored' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_*/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__cored' in the same scope was earlier saved to the database. has 1800 failures:

Test xbar_smoke has 100 failures.

0.xbar_smoke.66414161937656516993527403931569827000985686221712674860645830622598474794020
Line 248, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.xbar_smoke/latest/run.log

  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__cored' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__cored' in the same scope was earlier saved to the database.
  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__corei' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__corei' in the same scope was earlier saved to the database.
  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_dm__sba' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_dm__sba' in the same scope was earlier saved to the database.
  xmsim: *W,COVNBT: (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:281): Name of named block scope "gen_h2d" shall not be suffixed with a redundant "_T" in IMC type-based coverage in subsequent release in default mode. There may be other such named block scopes in the design.

1.xbar_smoke.50502374384082631411107327096694765381705895878551542475078229856621243456111
Line 248, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/1.xbar_smoke/latest/run.log

  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__cored' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__cored' in the same scope was earlier saved to the database.
  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__corei' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__corei' in the same scope was earlier saved to the database.
  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_dm__sba' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_dm__sba' in the same scope was earlier saved to the database.
  xmsim: *W,COVNBT: (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:281): Name of named block scope "gen_h2d" shall not be suffixed with a redundant "_T" in IMC type-based coverage in subsequent release in default mode. There may be other such named block scopes in the design.

... and 98 more failures.

Test xbar_smoke_zero_delays has 100 failures.

0.xbar_smoke_zero_delays.106957050156223734181253848606211367022363424078727727908010992612834445405399
Line 248, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.xbar_smoke_zero_delays/latest/run.log

  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__cored' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__cored' in the same scope was earlier saved to the database.
  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__corei' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__corei' in the same scope was earlier saved to the database.
  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_dm__sba' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_dm__sba' in the same scope was earlier saved to the database.
  xmsim: *W,COVNBT: (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:281): Name of named block scope "gen_h2d" shall not be suffixed with a redundant "_T" in IMC type-based coverage in subsequent release in default mode. There may be other such named block scopes in the design.

1.xbar_smoke_zero_delays.83179262974256968057499271715617078656066304527754820712843412960807184663530
Line 248, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/1.xbar_smoke_zero_delays/latest/run.log

  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__cored' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__cored' in the same scope was earlier saved to the database.
  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__corei' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__corei' in the same scope was earlier saved to the database.
  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_dm__sba' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_dm__sba' in the same scope was earlier saved to the database.
  xmsim: *W,COVNBT: (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:281): Name of named block scope "gen_h2d" shall not be suffixed with a redundant "_T" in IMC type-based coverage in subsequent release in default mode. There may be other such named block scopes in the design.

... and 98 more failures.

Test xbar_smoke_large_delays has 100 failures.

0.xbar_smoke_large_delays.79064095082296163650978212326496782291816081268287091041540398956120931490567
Line 248, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.xbar_smoke_large_delays/latest/run.log

  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__cored' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__cored' in the same scope was earlier saved to the database.
  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__corei' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__corei' in the same scope was earlier saved to the database.
  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_dm__sba' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_dm__sba' in the same scope was earlier saved to the database.
  xmsim: *W,COVNBT: (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:281): Name of named block scope "gen_h2d" shall not be suffixed with a redundant "_T" in IMC type-based coverage in subsequent release in default mode. There may be other such named block scopes in the design.

1.xbar_smoke_large_delays.68666432693468704919519728174694789466629226948453701527285204877660268295684
Line 248, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/1.xbar_smoke_large_delays/latest/run.log

  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__cored' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__cored' in the same scope was earlier saved to the database.
  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__corei' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__corei' in the same scope was earlier saved to the database.
  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_dm__sba' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_dm__sba' in the same scope was earlier saved to the database.
  xmsim: *W,COVNBT: (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:281): Name of named block scope "gen_h2d" shall not be suffixed with a redundant "_T" in IMC type-based coverage in subsequent release in default mode. There may be other such named block scopes in the design.

... and 98 more failures.

Test xbar_smoke_slow_rsp has 100 failures.

0.xbar_smoke_slow_rsp.53328226241666560437154088041858281192244764472470565407310009933706157872882
Line 248, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.xbar_smoke_slow_rsp/latest/run.log

  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__cored' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__cored' in the same scope was earlier saved to the database.
  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__corei' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__corei' in the same scope was earlier saved to the database.
  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_dm__sba' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_dm__sba' in the same scope was earlier saved to the database.
  xmsim: *W,COVNBT: (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:281): Name of named block scope "gen_h2d" shall not be suffixed with a redundant "_T" in IMC type-based coverage in subsequent release in default mode. There may be other such named block scopes in the design.

1.xbar_smoke_slow_rsp.20668542685858243608490416773150426217169777302036302902377824899488383610748
Line 248, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/1.xbar_smoke_slow_rsp/latest/run.log

  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__cored' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__cored' in the same scope was earlier saved to the database.
  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__corei' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__corei' in the same scope was earlier saved to the database.
  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_dm__sba' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_dm__sba' in the same scope was earlier saved to the database.
  xmsim: *W,COVNBT: (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:281): Name of named block scope "gen_h2d" shall not be suffixed with a redundant "_T" in IMC type-based coverage in subsequent release in default mode. There may be other such named block scopes in the design.

... and 98 more failures.

Test xbar_random has 100 failures.

0.xbar_random.25946271318452725782834525477657809582548416427409937579910916727360368519091
Line 325, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.xbar_random/latest/run.log

  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__cored' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__cored' in the same scope was earlier saved to the database.
  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__corei' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__corei' in the same scope was earlier saved to the database.
  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_dm__sba' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_dm__sba' in the same scope was earlier saved to the database.
  xmsim: *W,COVNBT: (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:281): Name of named block scope "gen_h2d" shall not be suffixed with a redundant "_T" in IMC type-based coverage in subsequent release in default mode. There may be other such named block scopes in the design.

1.xbar_random.75829640647846120086970532778769076402567882959647769984624474010846109375026
Line 313, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/1.xbar_random/latest/run.log

  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__cored' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__cored' in the same scope was earlier saved to the database.
  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__corei' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__corei' in the same scope was earlier saved to the database.
  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_dm__sba' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_dm__sba' in the same scope was earlier saved to the database.
  xmsim: *W,COVNBT: (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:281): Name of named block scope "gen_h2d" shall not be suffixed with a redundant "_T" in IMC type-based coverage in subsequent release in default mode. There may be other such named block scopes in the design.

... and 98 more failures.

... and 13 more tests.

Job timed out after * minutes has 217 failures:
- Test chip_csr_aliasing has 5 failures.
  - 0.chip_csr_aliasing.34921596904241419972204738388129154203963088441743511080271251835364028164091
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_csr_aliasing/latest/run.log
```
  Job timed out after 180 minutes
```
  - 1.chip_csr_aliasing.76567001636328178960613872632492553177373606440769951838356423882053188730992
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/1.chip_csr_aliasing/latest/run.log
```
  Job timed out after 180 minutes
```
  - ... and 3 more failures.
- Test chip_sw_sleep_pwm_pulses has 3 failures.
  - 0.chip_sw_sleep_pwm_pulses.82346093975092236577975118103906352826395078246978557337490762063840206148674
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_sw_sleep_pwm_pulses/latest/run.log
```
  Job timed out after 60 minutes
```
  - 1.chip_sw_sleep_pwm_pulses.95195257974923746756327320452755006261582559915171305280149637474108477582001
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/1.chip_sw_sleep_pwm_pulses/latest/run.log
```
  Job timed out after 60 minutes
```
  - ... and 1 more failures.
- Test chip_sw_uart_tx_rx_bootstrap has 3 failures.
  - 0.chip_sw_uart_tx_rx_bootstrap.44907399065208807842375829690686768731738038087584893104604744294329998734511
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_sw_uart_tx_rx_bootstrap/latest/run.log
```
  Job timed out after 480 minutes
```
  - 1.chip_sw_uart_tx_rx_bootstrap.114234647543512114411268333696328828899081019159244528742453164577321378509522
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/1.chip_sw_uart_tx_rx_bootstrap/latest/run.log
```
  Job timed out after 480 minutes
```
  - ... and 1 more failures.
- Test chip_sw_usbdev_dpi has 1 failures.
  - 0.chip_sw_usbdev_dpi.72407100422235492624558096177755188282081989388981054711088458984410209033998
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_sw_usbdev_dpi/latest/run.log
```
  Job timed out after 120 minutes
```
- Test chip_sw_usbdev_config_host has 1 failures.
  - 0.chip_sw_usbdev_config_host.98831903514061379198778520395111709102522026333457366970698800980718704422914
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_sw_usbdev_config_host/latest/run.log
```
  Job timed out after 60 minutes
```
- ... and 77 more tests.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 90 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 90 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.77466763468644917280682396224793787493546842791517931698858192543861097879796
    Line 388, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3180.023230 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 3180.023230 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_alert_handler_lpg_sleep_mode_alerts.67106590806634958442000461216271194110732486629068341479203361766279772355218
    Line 382, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/1.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3060.214534 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 3060.214534 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 88 more failures.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.44442442358806226433954546264498167358144831607734207587211724474276543881119
    Line 671, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.83937546113810665583774106982039785816138730564974038566677473657841216460976
    Line 608, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.10979976480912853017366964055137694794472515467670911292962328140465548671758
    Line 632, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.81711145781005834635865244677463508747390431053130851884414139237022811976799
    Line 595, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.4038276704830373704628165677220910691978978718682008852722467347583535281956
    Line 598, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.

xmsim: *E,ASRTST (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_earlgrey_ip_pwrmgr_*/rtl/pwrmgr_slow_fsm.sv,362): (time * NS) Assertion IntRstReq_A has failed has 9 failures:

Test chip_sw_pwrmgr_deep_sleep_power_glitch_reset has 3 failures.

0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.46120087020517675815178147314637126659505906841046336022656619259794150209594
Line 396, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_earlgrey_ip_pwrmgr_0.1/rtl/pwrmgr_slow_fsm.sv,362): (time 2781927 NS) Assertion tb.dut.top_earlgrey.u_pwrmgr_aon.u_slow_fsm.IntRstReq_A has failed
  UVM_ERROR @ 2781.927000 us: (pwrmgr_slow_fsm.sv:362) [ASSERT FAILED] IntRstReq_A
  UVM_INFO @ 2781.927000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.11159836869651129733491341766439024435399209798096488786623657942049700762098
Line 394, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_earlgrey_ip_pwrmgr_0.1/rtl/pwrmgr_slow_fsm.sv,362): (time 3092088 NS) Assertion tb.dut.top_earlgrey.u_pwrmgr_aon.u_slow_fsm.IntRstReq_A has failed
  UVM_ERROR @ 3092.088000 us: (pwrmgr_slow_fsm.sv:362) [ASSERT FAILED] IntRstReq_A
  UVM_INFO @ 3092.088000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_sw_pwrmgr_random_sleep_power_glitch_reset has 2 failures.

0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.19617323135765743062623176420047245453575477555943177447575056089514189401566
Line 416, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_earlgrey_ip_pwrmgr_0.1/rtl/pwrmgr_slow_fsm.sv,362): (time 6202103 NS) Assertion tb.dut.top_earlgrey.u_pwrmgr_aon.u_slow_fsm.IntRstReq_A has failed
  UVM_ERROR @ 6202.103000 us: (pwrmgr_slow_fsm.sv:362) [ASSERT FAILED] IntRstReq_A
  UVM_INFO @ 6202.103000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.8005977256324523463411236982763713568630075026000886598115614705105957809691
Line 454, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_earlgrey_ip_pwrmgr_0.1/rtl/pwrmgr_slow_fsm.sv,362): (time 12651568 NS) Assertion tb.dut.top_earlgrey.u_pwrmgr_aon.u_slow_fsm.IntRstReq_A has failed
  UVM_ERROR @ 12651.568000 us: (pwrmgr_slow_fsm.sv:362) [ASSERT FAILED] IntRstReq_A
  UVM_INFO @ 12651.568000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_pwrmgr_main_power_glitch_reset has 2 failures.

1.chip_sw_pwrmgr_main_power_glitch_reset.43058315319839272408853252722955484661465372361288839771551256855366623692777
Line 391, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/1.chip_sw_pwrmgr_main_power_glitch_reset/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_earlgrey_ip_pwrmgr_0.1/rtl/pwrmgr_slow_fsm.sv,362): (time 3203979 NS) Assertion tb.dut.top_earlgrey.u_pwrmgr_aon.u_slow_fsm.IntRstReq_A has failed
  UVM_ERROR @ 3203.979000 us: (pwrmgr_slow_fsm.sv:362) [ASSERT FAILED] IntRstReq_A
  UVM_INFO @ 3203.979000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.chip_sw_pwrmgr_main_power_glitch_reset.115082885114780559531233270194738006201652394946686065875667575571171442974014
Line 391, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/2.chip_sw_pwrmgr_main_power_glitch_reset/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_earlgrey_ip_pwrmgr_0.1/rtl/pwrmgr_slow_fsm.sv,362): (time 3552044 NS) Assertion tb.dut.top_earlgrey.u_pwrmgr_aon.u_slow_fsm.IntRstReq_A has failed
  UVM_ERROR @ 3552.044000 us: (pwrmgr_slow_fsm.sv:362) [ASSERT FAILED] IntRstReq_A
  UVM_INFO @ 3552.044000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_pwrmgr_sleep_power_glitch_reset has 2 failures.

1.chip_sw_pwrmgr_sleep_power_glitch_reset.41676552985889742516822493627937920810520317566452277941727257951793130395368
Line 392, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/1.chip_sw_pwrmgr_sleep_power_glitch_reset/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_earlgrey_ip_pwrmgr_0.1/rtl/pwrmgr_slow_fsm.sv,362): (time 2351329 NS) Assertion tb.dut.top_earlgrey.u_pwrmgr_aon.u_slow_fsm.IntRstReq_A has failed
  UVM_ERROR @ 2351.329000 us: (pwrmgr_slow_fsm.sv:362) [ASSERT FAILED] IntRstReq_A
  UVM_INFO @ 2351.329000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.chip_sw_pwrmgr_sleep_power_glitch_reset.110333292796363852325246623454035639694025584396175931677534341835480795252211
Line 392, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/2.chip_sw_pwrmgr_sleep_power_glitch_reset/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_earlgrey_ip_pwrmgr_0.1/rtl/pwrmgr_slow_fsm.sv,362): (time 2869532 NS) Assertion tb.dut.top_earlgrey.u_pwrmgr_aon.u_slow_fsm.IntRstReq_A has failed
  UVM_ERROR @ 2869.532000 us: (pwrmgr_slow_fsm.sv:362) [ASSERT FAILED] IntRstReq_A
  UVM_INFO @ 2869.532000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Job returned non-zero exit code has 7 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 3 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.13968906179070613104289555151787193326342593012173637251099332527042229261852
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.232s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_pwrmgr_sleep_wake_5_bug.29126582994894925859064789828006741724251184553048141691873792962704154111183
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/1.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.251s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_self_hash has 3 failures.

0.rom_e2e_self_hash.65769788974151126688584979651248966370946484861383480674262942358999689942303
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 4.739s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_self_hash.99289988431420156710597395934964772039451802548515933764768800101020258520743
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/1.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 0.296s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test chip has 1 failures.

cov_merge
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/cov_merge/merged/cov_merge.log

  [Executing]:
  make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk cov_merge cov_merge_cmd=imc cov_merge_opts='-64bit -licqueue -exec /nightly/current_run/opentitan/hw/dv/tools/xcelium/cov_merge.tcl'

  [make]: cov_merge
  imc -64bit -licqueue -exec /nightly/current_run/opentitan/hw/dv/tools/xcelium/cov_merge.tcl
  *I,imc.tool.cov.version.diff: "There is a difference between the IMC tool version 22.09 and the coverage version 21.09-s006"
  Error: Cannot invoke "jdk.internal.platform.CgroupInfo.getMountPoint()" because "<parameter1>" is null
  Created log file /nightly/current_run/opentitan/startup.log
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:231: cov_merge] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.77948780153417857548963005209883650273696184378670875220660570101233895114737
    Line 646, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.42538262735772247986684681605282324971623140691325125645087019423708359042359
    Line 663, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.69566232324665287435481611672269998536286431009848474014507580547170655093587
    Line 655, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.41255432402925156555323931708537576040753621891021053336151194154616155879896
    Line 619, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.86634738411497357784352451095495884050170767343484465640066803065220957827851
    Line 650, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected *, got * has 3 failures:
- Test chip_sw_all_escalation_resets has 3 failures.
  - 0.chip_sw_all_escalation_resets.63527466376224555695674686006462599886808548864481166490302617714137512969428
    Line 441, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 2716.427782 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 2716.427782 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 40.chip_sw_all_escalation_resets.7312648506587891139780174320809430348291180832624257729625317086488273478003
    Line 390, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/40.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 2832.801609 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 2832.801609 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 3 failures:
- Test chip_sw_spi_device_pass_through_collision has 3 failures.
  - 0.chip_sw_spi_device_pass_through_collision.72122361328288214217513627611871311027116517066464505624612292405638107090260
    Line 395, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3352.624144 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3352.624144 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_spi_device_pass_through_collision.109249497514320856107912606764305923747612167609164840489158127229849609604110
    Line 391, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/1.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3605.111585 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3605.111585 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: *. has 3 failures:
- Test chip_sw_hmac_oneshot has 3 failures.
  - 0.chip_sw_hmac_oneshot.79001513681858018208500433121769132485146533625136442700838471927364732735026
    Line 418, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_sw_hmac_oneshot/latest/run.log
```
  UVM_ERROR @ 3005.027388 us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: 8000534a.
  UVM_INFO @ 3005.027388 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_hmac_oneshot.20506656291142761971036093784465784769074649268840162710602845691591694580491
    Line 385, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/1.chip_sw_hmac_oneshot/latest/run.log
```
  UVM_ERROR @ 3033.762280 us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: 8000534a.
  UVM_INFO @ 3033.762280 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:92) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 3 failures:
- Test chip_sw_power_idle_load has 3 failures.
  - 0.chip_sw_power_idle_load.25335791832528651704926545416678527859323501339646499106768285587679451339370
    Line 386, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 2954.532000 us: (chip_sw_power_idle_load_vseq.sv:92) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH0 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 2954.532000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_power_idle_load.70125403556878960328166739673120825639244030890465120109683057700060906468320
    Line 388, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/1.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 3658.820000 us: (chip_sw_power_idle_load_vseq.sv:92) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH0 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3658.820000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:115) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 3 failures:
- Test chip_sw_power_sleep_load has 3 failures.
  - 0.chip_sw_power_sleep_load.88001890442606393369942157256226953487674636705695588242481324167442579712056
    Line 399, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3342.035000 us: (chip_sw_power_sleep_load_vseq.sv:115) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH0 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3342.035000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_power_sleep_load.54230021741674414438512810868170225873001078076113054312085011332843190900986
    Line 393, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/1.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 4079.748000 us: (chip_sw_power_sleep_load_vseq.sv:115) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH0 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 4079.748000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:196) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 3 failures:
- Test chip_sw_power_virus has 3 failures.
  - 0.chip_sw_power_virus.31171924184827706665899096067544866516188826917217919942398109966044228550017
    Line 434, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 3486.395325 us: (chip_sw_power_virus_vseq.sv:196) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 3486.395325 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_power_virus.97530433819773904087652013953378230194376929523362732355122543542333644838591
    Line 430, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/1.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 3566.320586 us: (chip_sw_power_virus_vseq.sv:196) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 3566.320586 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:37) [chip_sw_rom_e2e_shutdown_output_vseq] Check failed "OpenTitan:*-*-* has 3 failures:

Test rom_e2e_shutdown_output has 3 failures.

0.rom_e2e_shutdown_output.83339398292805309740371955199535791040057253336911905523335178831545742342846
Line 435, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_shutdown_output/latest/run.log

  UVM_ERROR @ 8601.108835 us: (chip_sw_rom_e2e_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_shutdown_output_vseq] Check failed "OpenTitan:4001-0002-01
  BF" == "OpenTitan:4001-0002-01x0d
  "
  UVM_INFO @ 8601.108835 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.rom_e2e_shutdown_output.26480047220904298105124809830569812470232605048957025821535501022422704792595
Line 425, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/1.rom_e2e_shutdown_output/latest/run.log

  UVM_ERROR @ 9981.507887 us: (chip_sw_rom_e2e_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_shutdown_output_vseq] Check failed "OpenTitan:4001-0002-01
  BF" == "OpenTitan:4001-0002-01x0d
  "
  UVM_INFO @ 9981.507887 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.113211784097660727469743231074340604788245097201545660645888173829579979510332
    Line 607, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.88639009876082916213215344012053095945167658667833020876469659486350683100637
    Line 621, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.42998825391529814518261999202165041182048196844776438637653679748003644542279
    Line 563, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [*] vs *xz [z]) for MIO[*] has 2 failures:
- Test chip_sw_sleep_pin_mio_dio_val has 2 failures.
  - 0.chip_sw_sleep_pin_mio_dio_val.27301569477098251330865612718828418599683131686492688417095942653667628589652
    Line 571, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_sw_sleep_pin_mio_dio_val/latest/run.log
```
  UVM_ERROR @ 2985.236000 us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (0x0 [0] vs 0xz [z]) for MIO[30]
  UVM_INFO @ 2985.236000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_sleep_pin_mio_dio_val.30269730983293198635423809807509123277451774317467326204964174245524709038483
    Line 520, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/1.chip_sw_sleep_pin_mio_dio_val/latest/run.log
```
  UVM_ERROR @ 3521.655000 us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (0x0 [0] vs 0xz [z]) for MIO[30]
  UVM_INFO @ 3521.655000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Test chip_sw_pwrmgr_main_power_glitch_reset has 1 failures.

0.chip_sw_pwrmgr_main_power_glitch_reset.30129600805693981252259544559060148511661356541006966644675625966585922511208
Line 390, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_sw_pwrmgr_main_power_glitch_reset/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_earlgrey_ip_pwrmgr_0.1/rtl/pwrmgr_slow_fsm.sv,362): (time 3525064500 PS) Assertion tb.dut.top_earlgrey.u_pwrmgr_aon.u_slow_fsm.IntRstReq_A has failed
  UVM_ERROR @ 3525.064500 us: (pwrmgr_slow_fsm.sv:362) [ASSERT FAILED] IntRstReq_A
  UVM_INFO @ 3525.064500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_pwrmgr_sleep_power_glitch_reset has 1 failures.

0.chip_sw_pwrmgr_sleep_power_glitch_reset.19578819018743263071294426245878083479530764089886630840033876598709113060030
Line 393, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_sw_pwrmgr_sleep_power_glitch_reset/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_earlgrey_ip_pwrmgr_0.1/rtl/pwrmgr_slow_fsm.sv,362): (time 2724463500 PS) Assertion tb.dut.top_earlgrey.u_pwrmgr_aon.u_slow_fsm.IntRstReq_A has failed
  UVM_ERROR @ 2724.463500 us: (pwrmgr_slow_fsm.sv:362) [ASSERT FAILED] IntRstReq_A
  UVM_INFO @ 2724.463500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor has 2 failures:
- Test chip_sw_sysrst_ctrl_ec_rst_l has 2 failures.
  - 0.chip_sw_sysrst_ctrl_ec_rst_l.2306171006424293729991524598173153676772417527422118492465678449476807146283
    Line 394, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_sw_sysrst_ctrl_ec_rst_l/latest/run.log
```
  UVM_ERROR @ 12324.963160 us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor
  UVM_INFO @ 12324.963160 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.chip_sw_sysrst_ctrl_ec_rst_l.74269611180055062319550112685955826072411173222028580533605883043649095282397
    Line 400, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/2.chip_sw_sysrst_ctrl_ec_rst_l/latest/run.log
```
  UVM_ERROR @ 11109.696322 us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor
  UVM_INFO @ 11109.696322 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 2 failures:
- Test chip_sw_alert_test has 2 failures.
  - 0.chip_sw_alert_test.69731559028943963242045239437630141489374741643068948702889272080877794117633
    Line 382, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 3285.964740 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
  UVM_INFO @ 3285.964740 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.chip_sw_alert_test.63072877309797428821242147729947377759535860656978916734267791689872695898807
    Line 381, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/2.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 2501.651625 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
  UVM_INFO @ 2501.651625 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.67068011570218793120750429010083009915756656694139715282087721940361865137763
    Line 614, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.13376160550045097150905313273772836633345220640940885545687474376587904315291
    Line 662, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.32052609520312946443627612679498955748376110957713674773792529514143540878463
    Line 698, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.56145110520031082921065001187827820733321152843527901564482059618585825863243
    Line 582, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:556) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@175396) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_sw_rstmgr_cpu_info has 2 failures.

1.chip_sw_rstmgr_cpu_info.5365614228652284139098328247859630131739964441209608634627931499936985901966
Line 406, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/1.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 4442.471424 us: (cip_base_scoreboard.sv:556) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@175396) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4442.471424 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.chip_sw_rstmgr_cpu_info.108568131983871648942405293008657722917739416217403030418908199013180109352877
Line 406, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/2.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 3975.333003 us: (cip_base_scoreboard.sv:556) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@175396) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3975.333003 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_vseq.sv:594) virtual_sequencer [Alert %0s fired unexpectedly.] usbdev_fatal_fault has 2 failures:
- Test chip_sw_all_escalation_resets has 2 failures.
  - 21.chip_sw_all_escalation_resets.83307128925572186657157843557551838710222312819762867225012231063863896164012
    Line 390, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/21.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 3197.531028 us: (cip_base_vseq.sv:594) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] usbdev_fatal_fault
  UVM_INFO @ 3197.531028 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 37.chip_sw_all_escalation_resets.42039041667256557120649060708833692175199928505442401198066928799909021697910
    Line 392, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/37.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 2528.478930 us: (cip_base_vseq.sv:594) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] usbdev_fatal_fault
  UVM_INFO @ 2528.478930 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:556) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@175358) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.67673900029329197603006713199073425586396611236502341685358604797675146330134
Line 409, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 5123.592066 us: (cip_base_scoreboard.sv:556) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@175358) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 5123.592066 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:556) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@324749) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.30797334007953163552165223643961856692343603695834251815008494499018100448011
Line 208, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 3799.237736 us: (cip_base_scoreboard.sv:556) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@324749) { a_addr: 'h10634  a_data: 'h266998f7  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3a  a_opcode: 'h4  a_user: 'h1ae69  d_param: 'h0  d_source: 'h3a  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3799.237736 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.22008892876320191039804863672333679737807417413895977043843546702889761716968
    Line 690, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.88555005004376886989597862048222469489084246305567618440210367288810113640353
    Line 714, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (jtag_rv_debugger.sv:613) [debugger] Check failed dcsr.cause == exp_debug_cause (* [*] vs * [*]) has 1 failures:
- Test rom_e2e_jtag_debug_dev has 1 failures.
  - 0.rom_e2e_jtag_debug_dev.69586040528062214719625126623186520346626516136227447023078939511305699816791
    Line 473, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_jtag_debug_dev/latest/run.log
```
  UVM_ERROR @ 3911.986465 us: (jtag_rv_debugger.sv:613) [debugger] Check failed dcsr.cause == exp_debug_cause (0 [0x0] vs 2 [0x2])
  UVM_INFO @ 3911.986465 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:337)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 1.chip_sw_alert_test.33221316965766311171233335523141974855903973671043333789322921235698159165562
    Line 381, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/1.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 2925.496050 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:337)] CHECK-fail: Expect alert 25!
  UVM_INFO @ 2925.496050 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:556) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@176365) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

1.chip_tl_errors.85376241538235107459896899892090337927817940979252864388012671704009258967753
Line 207, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/1.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2774.890376 us: (cip_base_scoreboard.sv:556) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@176365) { a_addr: 'h104a0  a_data: 'h890df811  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h33  a_opcode: 'h4  a_user: 'h1bda8  d_param: 'h0  d_source: 'h33  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2774.890376 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_sensor_ctrl_deep_sleep_wake_up_sim_dv(sw/device/tests/pwrmgr_sensor_ctrl_deep_sleep_wake_up.c:120)] CHECK-STATUS-fail: @@@:* = ErrorError has 1 failures:
- Test chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up has 1 failures.
  - 1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.65532837437157722768775982116282036047627032214149448301438609445743242156305
    Line 399, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest/run.log
```
  UVM_ERROR @ 6516.838186 us: (sw_logger_if.sv:526) [pwrmgr_sensor_ctrl_deep_sleep_wake_up_sim_dv(sw/device/tests/pwrmgr_sensor_ctrl_deep_sleep_wake_up.c:120)] CHECK-STATUS-fail: @@@:0 = ErrorError
  UVM_INFO @ 6516.838186 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_lc_raw_unlock_vseq.sv:78) [chip_sw_lc_raw_unlock_vseq] Timed out waiting for clkmgr to confirm extclk enablement has 1 failures:
- Test rom_raw_unlock has 1 failures.
  - 1.rom_raw_unlock.14951568729379983322698130120398028457481615425355596950073658904899974511186
    Line 428, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/1.rom_raw_unlock/latest/run.log
```
  UVM_FATAL @ 16610.117570 us: (chip_sw_lc_raw_unlock_vseq.sv:78) [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] Timed out waiting for clkmgr to confirm extclk enablement
  UVM_INFO @ 16610.117570 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:556) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@175963) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

1.chip_csr_mem_rw_with_rand_reset.2541124369668556011536569783912243303701509423235227740898336692211897465810
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/1.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2322.711455 us: (cip_base_scoreboard.sv:556) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@175963) { a_addr: 'h107e4  a_data: 'h5fd99acc  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'he  a_opcode: 'h4  a_user: 'h195e6  d_param: 'h0  d_source: 'he  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2322.711455 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:556) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@175997) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

2.chip_tl_errors.106838874728515968756675370991853039450476593810174010899523213069286663819005
Line 207, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/2.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2133.813134 us: (cip_base_scoreboard.sv:556) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@175997) { a_addr: 'h10610  a_data: 'hd0b0287  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h28  a_opcode: 'h4  a_user: 'h1ba2e  d_param: 'h0  d_source: 'h28  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2133.813134 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:715) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 1 failures:
- Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.
  - 2.chip_sw_rv_core_ibex_lockstep_glitch.13910427504657568422331190600111018567028411215736114540996739599843652558570
    Line 395, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/2.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
```
  UVM_FATAL @ 2612.254828 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:715) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
  UVM_INFO @ 2612.254828 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:37) [chip_sw_rom_e2e_shutdown_exception_c_vseq] Check failed "OpenTitan:*-*-* has 1 failures:
- Test rom_e2e_shutdown_exception_c has 1 failures.
  - 2.rom_e2e_shutdown_exception_c.74125457257004356520938038515570984593550573153778765691679418523935497657136
    Line 404, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/2.rom_e2e_shutdown_exception_c/latest/run.log
```
  UVM_ERROR @ 14795.980131 us: (chip_sw_rom_e2e_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_shutdown_exception_c_vseq] Check failed "OpenTitan:4001-0002-01
  BF" == "OpenTitan:4001-0002-01x0d
  "
  UVM_INFO @ 14795.980131 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:556) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@175894) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

2.chip_csr_mem_rw_with_rand_reset.21871675558440183000456428625739908909495184555406088682646594090096626618767
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/2.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2173.535692 us: (cip_base_scoreboard.sv:556) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@175894) { a_addr: 'h10628  a_data: 'h955d5e5e  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h32  a_opcode: 'h4  a_user: 'h192e0  d_param: 'h0  d_source: 'h32  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2173.535692 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:556) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@178341) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

3.chip_tl_errors.43062319841293042336827608379880981777897965904552126244539885902785310332698
Line 207, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/3.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2636.438840 us: (cip_base_scoreboard.sv:556) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@178341) { a_addr: 'h10724  a_data: 'hdf6a18a  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2b  a_opcode: 'h4  a_user: 'h18dbc  d_param: 'h0  d_source: 'h2b  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2636.438840 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:556) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@184880) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

5.chip_tl_errors.103582006723005377527619298093451391688664167864222383475366545289552816599153
Line 207, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/5.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2563.458875 us: (cip_base_scoreboard.sv:556) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@184880) { a_addr: 'h1068c  a_data: 'h41ab22ff  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2d  a_opcode: 'h4  a_user: 'h1b665  d_param: 'h0  d_source: 'h2d  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2563.458875 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:556) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@181705) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

6.chip_tl_errors.14109020187701318485607585879787307824784450144852094075073448232920342512869
Line 207, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/6.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2329.488307 us: (cip_base_scoreboard.sv:556) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@181705) { a_addr: 'h10348  a_data: 'h39de3aae  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h24  a_opcode: 'h4  a_user: 'h1b686  d_param: 'h0  d_source: 'h24  d_data: 'h13  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd7d  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2329.488307 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:556) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@175934) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

6.chip_csr_mem_rw_with_rand_reset.86150130504047870966488267474414965205125181889431396874860882311175037882071
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/6.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2314.844616 us: (cip_base_scoreboard.sv:556) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@175934) { a_addr: 'h1074c  a_data: 'hb5b808a9  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3e  a_opcode: 'h4  a_user: 'h1a931  d_param: 'h0  d_source: 'h3e  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2314.844616 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:556) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@176226) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

7.chip_tl_errors.76343772173734527752872020631215620461697269888652475450489980582302722669395
Line 207, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/7.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2293.210440 us: (cip_base_scoreboard.sv:556) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@176226) { a_addr: 'h10450  a_data: 'h4f148ee4  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h16  a_opcode: 'h4  a_user: 'h199c8  d_param: 'h0  d_source: 'h16  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2293.210440 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:556) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@184619) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

9.chip_tl_errors.76926056862993847213001310430690191077972663484901716430707487572414200926248
Line 207, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/9.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2357.591604 us: (cip_base_scoreboard.sv:556) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@184619) { a_addr: 'h10464  a_data: 'ha5420a6d  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2a  a_opcode: 'h4  a_user: 'h1a963  d_param: 'h0  d_source: 'h2a  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2357.591604 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:556) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@186314) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

9.chip_csr_mem_rw_with_rand_reset.102664578355620807468183483987919826623418703274700446956713686105455250432926
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/9.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2399.532625 us: (cip_base_scoreboard.sv:556) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@186314) { a_addr: 'h77c  a_data: 'hd6109456  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h18  a_opcode: 'h0  a_user: 'h25ec8  d_param: 'h0  d_source: 'h18  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2399.532625 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:556) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@181155) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

11.chip_tl_errors.10409976524832003186320052151347746652017265588359146699643416270752326745649
Line 207, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/11.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2489.257976 us: (cip_base_scoreboard.sv:556) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@181155) { a_addr: 'h10528  a_data: 'h611c5f8d  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1e  a_opcode: 'h4  a_user: 'h19efc  d_param: 'h0  d_source: 'h1e  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2489.257976 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:556) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@269210) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

11.chip_csr_mem_rw_with_rand_reset.114962558221899662216922686549921906357232741411200038954763833128929500339395
Line 230, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/11.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 5359.311036 us: (cip_base_scoreboard.sv:556) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@269210) { a_addr: 'h107dc  a_data: 'hfa33b8e  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h9  a_opcode: 'h4  a_user: 'h1bd22  d_param: 'h0  d_source: 'h9  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 5359.311036 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:556) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@175830) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

12.chip_tl_errors.8526659785533948717917466522326873655439768880904853405814403772413189866421
Line 207, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/12.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2125.172325 us: (cip_base_scoreboard.sv:556) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@175830) { a_addr: 'h10678  a_data: 'h266d3964  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h18  a_opcode: 'h4  a_user: 'h19ea4  d_param: 'h0  d_source: 'h18  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2125.172325 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:556) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@176410) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

12.chip_csr_mem_rw_with_rand_reset.58722533103578627716787186795209877800576142245247368044203801328276943027247
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/12.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2733.923997 us: (cip_base_scoreboard.sv:556) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@176410) { a_addr: 'h10568  a_data: 'h9220e488  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1d  a_opcode: 'h4  a_user: 'h1b640  d_param: 'h0  d_source: 'h1d  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2733.923997 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:556) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@176102) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

13.chip_tl_errors.13545761022428084233330470433838757212799817877378371097326650097964104245018
Line 207, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/13.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2240.074200 us: (cip_base_scoreboard.sv:556) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@176102) { a_addr: 'h107f4  a_data: 'ha6213f42  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1c  a_opcode: 'h4  a_user: 'h1b154  d_param: 'h0  d_source: 'h1c  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2240.074200 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:556) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@176700) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

14.chip_tl_errors.65651138763549442406159111642400929042384796082429222845884227963728400265583
Line 207, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/14.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2317.399913 us: (cip_base_scoreboard.sv:556) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@176700) { a_addr: 'h106a8  a_data: 'hfa8ed157  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h36  a_opcode: 'h4  a_user: 'h1a221  d_param: 'h0  d_source: 'h36  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2317.399913 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:556) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@176400) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

14.chip_csr_mem_rw_with_rand_reset.3485721211223441090706096160127461768992862103633069270796812815615865350027
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/14.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 1659.147531 us: (cip_base_scoreboard.sv:556) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@176400) { a_addr: 'h107d0  a_data: 'h9c7cf8d3  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h31  a_opcode: 'h4  a_user: 'h1a57b  d_param: 'h0  d_source: 'h31  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 1659.147531 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:556) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@176548) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

15.chip_csr_mem_rw_with_rand_reset.61289721666091974614721514763350143867791368227612154103824448910622438293476
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/15.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 1918.728360 us: (cip_base_scoreboard.sv:556) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@176548) { a_addr: 'h10448  a_data: 'hef252103  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h29  a_opcode: 'h4  a_user: 'h1a9b7  d_param: 'h0  d_source: 'h29  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 1918.728360 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:556) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@179887) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

16.chip_tl_errors.72971219046548107792046417543663879480868108586679659949180021242936705562299
Line 207, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/16.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2905.482975 us: (cip_base_scoreboard.sv:556) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@179887) { a_addr: 'h1076c  a_data: 'h2038e339  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h6  a_opcode: 'h4  a_user: 'h1b1ec  d_param: 'h0  d_source: 'h6  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2905.482975 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:556) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@183094) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

18.chip_tl_errors.61050374855443157833903512811877249090859652084990576744922466589869255581563
Line 207, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/18.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2477.569866 us: (cip_base_scoreboard.sv:556) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@183094) { a_addr: 'h106a4  a_data: 'hd9716243  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h26  a_opcode: 'h4  a_user: 'h1ba48  d_param: 'h0  d_source: 'h26  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2477.569866 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:556) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@185963) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

18.chip_csr_mem_rw_with_rand_reset.59543849258173626891040290567655022934814541468499367988323899431589372048027
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/18.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2200.071790 us: (cip_base_scoreboard.sv:556) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@185963) { a_addr: 'haf4  a_data: 'hc029c411  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h11  a_opcode: 'h1  a_user: 'h26c7f  d_param: 'h0  d_source: 'h11  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2200.071790 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:556) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@180224) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

19.chip_tl_errors.70225662749090055151644250673586340245296316693741605191417805387805705313235
Line 207, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/19.chip_tl_errors/latest/run.log

  UVM_ERROR @ 1911.126200 us: (cip_base_scoreboard.sv:556) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@180224) { a_addr: 'h107ac  a_data: 'h7ad30676  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h4  a_user: 'h1a9dc  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 1911.126200 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:556) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@179215) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

19.chip_csr_mem_rw_with_rand_reset.23799948804235619930988951207145637293896400059045591662848888966691700180754
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/19.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2145.665200 us: (cip_base_scoreboard.sv:556) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@179215) { a_addr: 'h11ac  a_data: 'h9b1d7b9  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h13  a_opcode: 'h1  a_user: 'h256e6  d_param: 'h0  d_source: 'h13  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2145.665200 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:556) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@180155) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

21.chip_tl_errors.102398649991191472752632290862525797443189759929423055758372426901403485699878
Line 207, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/21.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2787.856964 us: (cip_base_scoreboard.sv:556) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@180155) { a_addr: 'h10448  a_data: 'had180077  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2e  a_opcode: 'h4  a_user: 'h1a9d5  d_param: 'h0  d_source: 'h2e  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2787.856964 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:556) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@184055) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

22.chip_tl_errors.102622018594171201648595819601893823066033655204547309463868513426329088494088
Line 208, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/22.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2629.726622 us: (cip_base_scoreboard.sv:556) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@184055) { a_addr: 'h1073c  a_data: 'hb50ebdbd  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h32  a_opcode: 'h4  a_user: 'h1bdf5  d_param: 'h0  d_source: 'h32  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2629.726622 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:556) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@183809) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

23.chip_tl_errors.105762210554464344176609132624356817156758834926724009237915588322488729559674
Line 207, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/23.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2689.512304 us: (cip_base_scoreboard.sv:556) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@183809) { a_addr: 'h104f4  a_data: 'h7c31eab2  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3c  a_opcode: 'h4  a_user: 'h1bd36  d_param: 'h0  d_source: 'h3c  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2689.512304 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:556) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@184938) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

24.chip_tl_errors.85044835792141361580045715465907981187668333199555187221729348617027336245638
Line 208, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/24.chip_tl_errors/latest/run.log

  UVM_ERROR @ 4001.044525 us: (cip_base_scoreboard.sv:556) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@184938) { a_addr: 'h10628  a_data: 'had608064  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'ha  a_opcode: 'h4  a_user: 'h1929b  d_param: 'h0  d_source: 'ha  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4001.044525 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:556) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@181430) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

25.chip_tl_errors.26724997850332998421564936689378478288908236346430174509701532220747970073123
Line 207, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/25.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2780.343656 us: (cip_base_scoreboard.sv:556) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@181430) { a_addr: 'h106cc  a_data: 'h1aed5daa  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h28  a_opcode: 'h4  a_user: 'h19ec3  d_param: 'h0  d_source: 'h28  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2780.343656 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:556) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@188571) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

28.chip_tl_errors.53648042803625790521474670821758095877817162189373112014833807580526156779339
Line 207, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/28.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2331.086836 us: (cip_base_scoreboard.sv:556) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@188571) { a_addr: 'h105e0  a_data: 'hdd97c57b  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h29  a_opcode: 'h4  a_user: 'h19230  d_param: 'h0  d_source: 'h29  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2331.086836 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:556) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@176087) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

29.chip_tl_errors.111020941440778421750657257152657037500055299361932176576527827612481179909995
Line 207, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/29.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2147.621350 us: (cip_base_scoreboard.sv:556) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@176087) { a_addr: 'h10344  a_data: 'h8b6e979c  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h37  a_opcode: 'h4  a_user: 'h1aeb2  d_param: 'h0  d_source: 'h37  d_data: 'hc51513  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd5b  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2147.621350 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Job killed most likely because its dependent job failed. has 1 failures:
- Test chip has 1 failures.
  - cov_report
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/cov_report/cov_report.log