a99e70f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | adc_ctrl_smoke | 8.000s | 6.034ms | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | adc_ctrl_csr_hw_reset | 12.000s | 840.162us | 1 | 1 | 100.00 |
| V1 | csr_rw | adc_ctrl_csr_rw | 5.000s | 372.793us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | adc_ctrl_csr_bit_bash | 23.000s | 17.521ms | 0 | 1 | 0.00 |
| V1 | csr_aliasing | adc_ctrl_csr_aliasing | 4.000s | 867.845us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | adc_ctrl_csr_mem_rw_with_rand_reset | 3.000s | 344.658us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | adc_ctrl_csr_rw | 5.000s | 372.793us | 1 | 1 | 100.00 |
| adc_ctrl_csr_aliasing | 4.000s | 867.845us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 5 | 6 | 83.33 | |||
| V2 | filters_polled | adc_ctrl_filters_polled | 29.183m | 495.246ms | 1 | 1 | 100.00 |
| V2 | filters_polled_fixed | adc_ctrl_filters_polled_fixed | 2.517m | 497.130ms | 1 | 1 | 100.00 |
| V2 | filters_interrupt | adc_ctrl_filters_interrupt | 3.067m | 163.136ms | 1 | 1 | 100.00 |
| V2 | filters_interrupt_fixed | adc_ctrl_filters_interrupt_fixed | 2.767m | 168.043ms | 1 | 1 | 100.00 |
| V2 | filters_wakeup | adc_ctrl_filters_wakeup | 18.783m | 350.797ms | 1 | 1 | 100.00 |
| V2 | filters_wakeup_fixed | adc_ctrl_filters_wakeup_fixed | 5.700m | 394.096ms | 1 | 1 | 100.00 |
| V2 | filters_both | adc_ctrl_filters_both | 18.067m | 346.070ms | 1 | 1 | 100.00 |
| V2 | clock_gating | adc_ctrl_clock_gating | 30.633m | 524.894ms | 1 | 1 | 100.00 |
| V2 | poweron_counter | adc_ctrl_poweron_counter | 23.000s | 4.472ms | 1 | 1 | 100.00 |
| V2 | lowpower_counter | adc_ctrl_lowpower_counter | 27.000s | 27.027ms | 1 | 1 | 100.00 |
| V2 | fsm_reset | adc_ctrl_fsm_reset | 3.000s | 374.572us | 0 | 1 | 0.00 |
| V2 | stress_all | adc_ctrl_stress_all | 33.033m | 651.578ms | 1 | 1 | 100.00 |
| V2 | alert_test | adc_ctrl_alert_test | 4.000s | 378.869us | 1 | 1 | 100.00 |
| V2 | intr_test | adc_ctrl_intr_test | 4.000s | 392.694us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | adc_ctrl_tl_errors | 5.000s | 506.822us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | adc_ctrl_tl_errors | 5.000s | 506.822us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | adc_ctrl_csr_hw_reset | 12.000s | 840.162us | 1 | 1 | 100.00 |
| adc_ctrl_csr_rw | 5.000s | 372.793us | 1 | 1 | 100.00 | ||
| adc_ctrl_csr_aliasing | 4.000s | 867.845us | 1 | 1 | 100.00 | ||
| adc_ctrl_same_csr_outstanding | 19.000s | 4.062ms | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | adc_ctrl_csr_hw_reset | 12.000s | 840.162us | 1 | 1 | 100.00 |
| adc_ctrl_csr_rw | 5.000s | 372.793us | 1 | 1 | 100.00 | ||
| adc_ctrl_csr_aliasing | 4.000s | 867.845us | 1 | 1 | 100.00 | ||
| adc_ctrl_same_csr_outstanding | 19.000s | 4.062ms | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 15 | 16 | 93.75 | |||
| V2S | tl_intg_err | adc_ctrl_sec_cm | 31.000s | 7.892ms | 1 | 1 | 100.00 |
| adc_ctrl_tl_intg_err | 5.000s | 4.557ms | 1 | 1 | 100.00 | ||
| V2S | sec_cm_bus_integrity | adc_ctrl_tl_intg_err | 5.000s | 4.557ms | 1 | 1 | 100.00 |
| V2S | TOTAL | 2 | 2 | 100.00 | |||
| V3 | stress_all_with_rand_reset | adc_ctrl_stress_all_with_rand_reset | 6.000s | 946.634us | 0 | 1 | 0.00 |
| V3 | TOTAL | 0 | 1 | 0.00 | |||
| TOTAL | 22 | 25 | 88.00 |
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/adc_ctrl-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_adc_ctrl_*/rtl/adc_ctrl_fsm.sv,385): (time * NS) Assertion NpCntClrPwrDn_A has failed has 1 failures:
0.adc_ctrl_fsm_reset.85145683584706051222048634812626900957066648380100209328407421856090489732893
Line 166, in log /nightly/current_run/scratch/master/adc_ctrl-sim-xcelium/0.adc_ctrl_fsm_reset/latest/run.log
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/adc_ctrl-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_fsm.sv,385): (time 374572 NS) Assertion tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.NpCntClrPwrDn_A has failed
UVM_ERROR @ 374572000 ps: (adc_ctrl_fsm.sv:385) [ASSERT FAILED] NpCntClrPwrDn_A
UVM_INFO @ 374572000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/adc_ctrl-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_adc_ctrl_*/rtl/adc_ctrl_fsm.sv,385): Assertion NpCntClrPwrDn_A has failed has 1 failures:
0.adc_ctrl_stress_all_with_rand_reset.111767210924631676068639017415816218825762693318177937242965190892659862120080
Line 190, in log /nightly/current_run/scratch/master/adc_ctrl-sim-xcelium/0.adc_ctrl_stress_all_with_rand_reset/latest/run.log
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/adc_ctrl-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_fsm.sv,385): (time 946634271 PS) Assertion tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.NpCntClrPwrDn_A has failed
UVM_ERROR @ 946634271 ps: (adc_ctrl_fsm.sv:385) [ASSERT FAILED] NpCntClrPwrDn_A
UVM_INFO @ 946634271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/adc_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_ip_adc_ctrl_*/rtl/adc_ctrl_fsm.sv,382): Assertion LpSampleCntCfg_M has failed has 1 failures:
0.adc_ctrl_csr_bit_bash.109959850461667437233130748585335839601848389084066777151362815463432940202252
Line 163, in log /nightly/current_run/scratch/master/adc_ctrl-sim-xcelium/0.adc_ctrl_csr_bit_bash/latest/run.log
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/adc_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_fsm.sv,382): (time 17521200117 PS) Assertion tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.LpSampleCntCfg_M has failed
UVM_ERROR @ 17521200117 ps: (adc_ctrl_fsm.sv:382) [ASSERT FAILED] LpSampleCntCfg_M
UVM_INFO @ 17521200117 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---