| V1 |
smoke |
aon_timer_smoke |
4.000s |
519.935us |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
aon_timer_csr_hw_reset |
4.000s |
1.355ms |
1 |
1 |
100.00 |
| V1 |
csr_rw |
aon_timer_csr_rw |
3.000s |
407.754us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
aon_timer_csr_bit_bash |
15.000s |
7.789ms |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
aon_timer_csr_aliasing |
4.000s |
564.938us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
aon_timer_csr_mem_rw_with_rand_reset |
3.000s |
538.975us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
aon_timer_csr_rw |
3.000s |
407.754us |
1 |
1 |
100.00 |
|
|
aon_timer_csr_aliasing |
4.000s |
564.938us |
1 |
1 |
100.00 |
| V1 |
mem_walk |
aon_timer_mem_walk |
3.000s |
440.896us |
1 |
1 |
100.00 |
| V1 |
mem_partial_access |
aon_timer_mem_partial_access |
3.000s |
450.445us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
8 |
8 |
100.00 |
| V2 |
prescaler |
aon_timer_prescaler |
4.000s |
535.398us |
1 |
1 |
100.00 |
| V2 |
jump |
aon_timer_jump |
4.000s |
600.811us |
1 |
1 |
100.00 |
| V2 |
stress_all |
aon_timer_stress_all |
25.000s |
18.785ms |
1 |
1 |
100.00 |
| V2 |
alert_test |
aon_timer_alert_test |
4.000s |
489.533us |
1 |
1 |
100.00 |
| V2 |
intr_test |
aon_timer_intr_test |
4.000s |
303.393us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
aon_timer_tl_errors |
7.000s |
516.137us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
aon_timer_tl_errors |
7.000s |
516.137us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
aon_timer_csr_hw_reset |
4.000s |
1.355ms |
1 |
1 |
100.00 |
|
|
aon_timer_csr_rw |
3.000s |
407.754us |
1 |
1 |
100.00 |
|
|
aon_timer_csr_aliasing |
4.000s |
564.938us |
1 |
1 |
100.00 |
|
|
aon_timer_same_csr_outstanding |
4.000s |
1.147ms |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
aon_timer_csr_hw_reset |
4.000s |
1.355ms |
1 |
1 |
100.00 |
|
|
aon_timer_csr_rw |
3.000s |
407.754us |
1 |
1 |
100.00 |
|
|
aon_timer_csr_aliasing |
4.000s |
564.938us |
1 |
1 |
100.00 |
|
|
aon_timer_same_csr_outstanding |
4.000s |
1.147ms |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
7 |
7 |
100.00 |
| V2S |
tl_intg_err |
aon_timer_sec_cm |
27.000s |
8.129ms |
1 |
1 |
100.00 |
|
|
aon_timer_tl_intg_err |
9.000s |
8.238ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
aon_timer_tl_intg_err |
9.000s |
8.238ms |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
2 |
2 |
100.00 |
| V3 |
max_threshold |
aon_timer_smoke_max_thold |
5.000s |
683.707us |
1 |
1 |
100.00 |
| V3 |
min_threshold |
aon_timer_smoke_min_thold |
4.000s |
626.951us |
1 |
1 |
100.00 |
| V3 |
wkup_count_hi_cdc |
aon_timer_wkup_count_cdc_hi |
10.000s |
3.083ms |
1 |
1 |
100.00 |
| V3 |
custom_intr |
aon_timer_custom_intr |
5.000s |
717.005us |
1 |
1 |
100.00 |
| V3 |
alternating_on_off |
aon_timer_alternating_enable_on_off |
5.000s |
4.426ms |
1 |
1 |
100.00 |
| V3 |
stress_all_with_rand_reset |
aon_timer_stress_all_with_rand_reset |
21.000s |
2.698ms |
1 |
1 |
100.00 |
| V3 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
|
|
TOTAL |
|
|
23 |
23 |
100.00 |