EDN Simulation Results

Friday September 12 2025 11:15:38 UTC

GitHub Revision: a99e70f

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	3.000s	25.507us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	3.000s	53.148us	1	1	100.00
V1	csr_rw	edn_csr_rw	3.000s	14.956us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	4.000s	85.226us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	4.000s	37.610us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	3.000s	77.034us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	3.000s	14.956us	1	1	100.00
		edn_csr_aliasing	4.000s	37.610us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	2.000s	76.241us	1	1	100.00
V2	csrng_commands	edn_genbits	2.000s	76.241us	1	1	100.00
V2	genbits	edn_genbits	2.000s	76.241us	1	1	100.00
V2	interrupts	edn_intr	2.000s	11.672us	0	1	0.00
V2	alerts	edn_alert	3.000s	28.593us	1	1	100.00
V2	errs	edn_err	2.000s	3.295us	0	1	0.00
V2	disable	edn_disable	2.000s	118.113us	1	1	100.00
		edn_disable_auto_req_mode	3.000s	122.139us	1	1	100.00
V2	stress_all	edn_stress_all	5.000s	540.494us	1	1	100.00
V2	intr_test	edn_intr_test	3.000s	31.286us	1	1	100.00
V2	alert_test	edn_alert_test	3.000s	15.943us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	5.000s	102.687us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	5.000s	102.687us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	3.000s	53.148us	1	1	100.00
		edn_csr_rw	3.000s	14.956us	1	1	100.00
		edn_csr_aliasing	4.000s	37.610us	1	1	100.00
		edn_same_csr_outstanding	3.000s	33.673us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	3.000s	53.148us	1	1	100.00
		edn_csr_rw	3.000s	14.956us	1	1	100.00
		edn_csr_aliasing	4.000s	37.610us	1	1	100.00
		edn_same_csr_outstanding	3.000s	33.673us	1	1	100.00
V2		TOTAL			9	11	81.82
V2S	tl_intg_err	edn_sec_cm	6.000s	536.401us	1	1	100.00
		edn_tl_intg_err	4.000s	365.805us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	3.000s	44.760us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	3.000s	28.593us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	6.000s	536.401us	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	6.000s	536.401us	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	6.000s	536.401us	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	6.000s	536.401us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	3.000s	28.593us	1	1	100.00
		edn_sec_cm	6.000s	536.401us	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	3.000s	28.593us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	4.000s	365.805us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	2.350m	6.923ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			19	21	90.48

Failure Buckets

• xmsim: *E,ASRTST (/nightly/current_run/scratch/master/edn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_edn_*/rtl/edn_main_sm.sv,42): Assertion u_state_regs_A has failed has 1 failures:

  • Test edn_intr has 1 failures.

    • 0.edn_intr.61005015897485313115944699539949907174153611319821967769108192065058954821033
      Line 123, in log /nightly/current_run/scratch/master/edn-sim-xcelium/0.edn_intr/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/edn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv,42): (time 11671763 PS) Assertion tb.dut.u_edn_core.u_edn_main_sm.u_state_regs_A has failed
        UVM_ERROR @  11671763 ps: (edn_main_sm.sv:42) [ASSERT FAILED] u_state_regs_A
        UVM_INFO @  11671763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• xmsim: *E,ASRTST (/nightly/current_run/scratch/master/edn-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_count_*/rtl/prim_count.sv,300): Assertion CntErrReported_A has failed (* cycles, starting * PS) has 1 failures:

  • Test edn_err has 1 failures.

    • 0.edn_err.39008604489646185960118264187040392929193448731588854780129255178989297381710
      Line 144, in log /nightly/current_run/scratch/master/edn-sim-xcelium/0.edn_err/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/edn-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_count_0/rtl/prim_count.sv,300): (time 3295312 PS) Assertion tb.dut.u_edn_core.u_prim_count_max_reqs_cntr.CntErrReported_A has failed (2 cycles, starting 3285312 PS)
        UVM_ERROR @   3295312 ps: (prim_count.sv:300) [ASSERT FAILED] CntErrReported_A
        UVM_INFO @   3295312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---