HMAC Simulation Results

Friday September 12 2025 11:15:38 UTC

GitHub Revision: a99e70f

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 23.000s 6.751ms 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 3.000s 69.275us 1 1 100.00
V1 csr_rw hmac_csr_rw 3.000s 47.294us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 16.000s 645.622us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 8.000s 318.613us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 8.000m 140.362ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 3.000s 47.294us 1 1 100.00
hmac_csr_aliasing 8.000s 318.613us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 2.133m 1.814ms 1 1 100.00
V2 back_pressure hmac_back_pressure 1.783m 1.912ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 5.883m 7.159ms 1 1 100.00
hmac_test_sha384_vectors 43.000s 2.270ms 1 1 100.00
hmac_test_sha512_vectors 41.000s 307.721us 1 1 100.00
hmac_test_hmac256_vectors 13.000s 402.327us 1 1 100.00
hmac_test_hmac384_vectors 21.000s 721.528us 1 1 100.00
hmac_test_hmac512_vectors 27.000s 2.543ms 1 1 100.00
V2 burst_wr hmac_burst_wr 45.000s 7.180ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 8.717m 59.069ms 1 1 100.00
V2 error hmac_error 1.100m 14.589ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 56.000s 2.336ms 1 1 100.00
V2 save_and_restore hmac_smoke 23.000s 6.751ms 1 1 100.00
hmac_long_msg 2.133m 1.814ms 1 1 100.00
hmac_back_pressure 1.783m 1.912ms 1 1 100.00
hmac_datapath_stress 8.717m 59.069ms 1 1 100.00
hmac_burst_wr 45.000s 7.180ms 1 1 100.00
hmac_stress_all 5.950m 74.532ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 23.000s 6.751ms 1 1 100.00
hmac_long_msg 2.133m 1.814ms 1 1 100.00
hmac_back_pressure 1.783m 1.912ms 1 1 100.00
hmac_datapath_stress 8.717m 59.069ms 1 1 100.00
hmac_wipe_secret 56.000s 2.336ms 1 1 100.00
hmac_test_sha256_vectors 5.883m 7.159ms 1 1 100.00
hmac_test_sha384_vectors 43.000s 2.270ms 1 1 100.00
hmac_test_sha512_vectors 41.000s 307.721us 1 1 100.00
hmac_test_hmac256_vectors 13.000s 402.327us 1 1 100.00
hmac_test_hmac384_vectors 21.000s 721.528us 1 1 100.00
hmac_test_hmac512_vectors 27.000s 2.543ms 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 23.000s 6.751ms 1 1 100.00
hmac_long_msg 2.133m 1.814ms 1 1 100.00
hmac_back_pressure 1.783m 1.912ms 1 1 100.00
hmac_datapath_stress 8.717m 59.069ms 1 1 100.00
hmac_burst_wr 45.000s 7.180ms 1 1 100.00
hmac_error 1.100m 14.589ms 1 1 100.00
hmac_wipe_secret 56.000s 2.336ms 1 1 100.00
hmac_test_sha256_vectors 5.883m 7.159ms 1 1 100.00
hmac_test_sha384_vectors 43.000s 2.270ms 1 1 100.00
hmac_test_sha512_vectors 41.000s 307.721us 1 1 100.00
hmac_test_hmac256_vectors 13.000s 402.327us 1 1 100.00
hmac_test_hmac384_vectors 21.000s 721.528us 1 1 100.00
hmac_test_hmac512_vectors 27.000s 2.543ms 1 1 100.00
hmac_stress_all 5.950m 74.532ms 1 1 100.00
V2 stress_all hmac_stress_all 5.950m 74.532ms 1 1 100.00
V2 alert_test hmac_alert_test 3.000s 12.393us 1 1 100.00
V2 intr_test hmac_intr_test 3.000s 28.199us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 7.000s 1.335ms 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 7.000s 1.335ms 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 3.000s 69.275us 1 1 100.00
hmac_csr_rw 3.000s 47.294us 1 1 100.00
hmac_csr_aliasing 8.000s 318.613us 1 1 100.00
hmac_same_csr_outstanding 4.000s 94.741us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 3.000s 69.275us 1 1 100.00
hmac_csr_rw 3.000s 47.294us 1 1 100.00
hmac_csr_aliasing 8.000s 318.613us 1 1 100.00
hmac_same_csr_outstanding 4.000s 94.741us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 4.000s 125.599us 1 1 100.00
hmac_tl_intg_err 6.000s 179.816us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 6.000s 179.816us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 23.000s 6.751ms 1 1 100.00
V3 stress_reset hmac_stress_reset 4.000s 98.842us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 3.067m 16.141ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 8.000s 906.295us 1 1 100.00
TOTAL 28 28 100.00