a99e70f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 0 | 1 | 0.00 | ||
| V1 | target_smoke | i2c_target_smoke | 22.000s | 4.559ms | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 3.000s | 28.041us | 1 | 1 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 3.000s | 24.522us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 5.000s | 379.825us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 4.000s | 66.430us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 3.000s | 38.361us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 3.000s | 24.522us | 1 | 1 | 100.00 |
| i2c_csr_aliasing | 4.000s | 66.430us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 6 | 7 | 85.71 | |||
| V2 | host_error_intr | i2c_host_error_intr | 3.000s | 15.071us | 0 | 1 | 0.00 |
| V2 | host_stress_all | i2c_host_stress_all | 0 | 1 | 0.00 | ||
| V2 | host_maxperf | i2c_host_perf | 0 | 1 | 0.00 | ||
| V2 | host_override | i2c_host_override | 3.000s | 39.780us | 1 | 1 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 0 | 1 | 0.00 | ||
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 0 | 1 | 0.00 | ||
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 3.000s | 324.096us | 1 | 1 | 100.00 |
| i2c_host_fifo_fmt_empty | 0 | 1 | 0.00 | ||||
| i2c_host_fifo_reset_rx | 6.000s | 149.909us | 1 | 1 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 0 | 1 | 0.00 | ||
| V2 | host_timeout | i2c_host_stretch_timeout | 25.600m | 2.595ms | 1 | 1 | 100.00 |
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 17.000s | 78.721us | 0 | 1 | 0.00 |
| V2 | target_glitch | i2c_target_glitch | 7.000s | 2.069ms | 0 | 1 | 0.00 |
| V2 | target_stress_all | i2c_target_stress_all | 0 | 1 | 0.00 | ||
| V2 | target_maxperf | i2c_target_perf | 0 | 1 | 0.00 | ||
| V2 | target_fifo_empty | i2c_target_stress_rd | 0 | 1 | 0.00 | ||
| i2c_target_intr_smoke | 0 | 1 | 0.00 | ||||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 16.000s | 286.822us | 1 | 1 | 100.00 |
| i2c_target_fifo_reset_tx | 35.000s | 194.986us | 1 | 1 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 0 | 1 | 0.00 | ||
| i2c_target_stress_rd | 0 | 1 | 0.00 | ||||
| i2c_target_intr_stress_wr | 0 | 1 | 0.00 | ||||
| V2 | target_timeout | i2c_target_timeout | 1.517m | 4.988ms | 1 | 1 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 0 | 1 | 0.00 | ||
| V2 | bad_address | i2c_target_bad_addr | 12.000s | 3.397ms | 1 | 1 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 7.000s | 10.394ms | 0 | 1 | 0.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 6.000s | 532.903us | 1 | 1 | 100.00 |
| i2c_target_fifo_watermarks_tx | 4.000s | 187.694us | 1 | 1 | 100.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 0 | 1 | 0.00 | ||
| i2c_host_perf_precise | 59.000s | 193.121us | 1 | 1 | 100.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 25.600m | 2.595ms | 1 | 1 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 10.000s | 523.119us | 1 | 1 | 100.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 10.000s | 2.002ms | 1 | 1 | 100.00 |
| i2c_target_nack_acqfull_addr | 26.000s | 504.821us | 1 | 1 | 100.00 | ||
| i2c_target_nack_txstretch | 50.433m | 263.733us | 1 | 1 | 100.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 10.000s | 460.237us | 1 | 1 | 100.00 |
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 6.000s | 907.997us | 1 | 1 | 100.00 |
| V2 | alert_test | i2c_alert_test | 3.000s | 17.016us | 1 | 1 | 100.00 |
| V2 | intr_test | i2c_intr_test | 3.000s | 114.515us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 4.000s | 189.478us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 4.000s | 189.478us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 3.000s | 28.041us | 1 | 1 | 100.00 |
| i2c_csr_rw | 3.000s | 24.522us | 1 | 1 | 100.00 | ||
| i2c_csr_aliasing | 4.000s | 66.430us | 1 | 1 | 100.00 | ||
| i2c_same_csr_outstanding | 3.000s | 71.838us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 3.000s | 28.041us | 1 | 1 | 100.00 |
| i2c_csr_rw | 3.000s | 24.522us | 1 | 1 | 100.00 | ||
| i2c_csr_aliasing | 4.000s | 66.430us | 1 | 1 | 100.00 | ||
| i2c_same_csr_outstanding | 3.000s | 71.838us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 21 | 38 | 55.26 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 5.000s | 170.892us | 1 | 1 | 100.00 |
| i2c_sec_cm | 3.000s | 237.532us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 5.000s | 170.892us | 1 | 1 | 100.00 |
| V2S | TOTAL | 2 | 2 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 0 | 1 | 0.00 | ||
| V3 | target_error_intr | i2c_target_unexp_stop | 3.000s | 67.284us | 0 | 1 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 16.000s | 1.405ms | 0 | 1 | 0.00 |
| V3 | TOTAL | 0 | 3 | 0.00 | |||
| TOTAL | 29 | 50 | 58.00 |
Job timed out after * minutes has 15 failures:
Test i2c_host_smoke has 1 failures.
0.i2c_host_smoke.92937851927615965148268025070666948151806483830716776942005803862963210994121
Log /nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_host_smoke/latest/run.log
Job timed out after 60 minutes
Test i2c_host_fifo_watermark has 1 failures.
0.i2c_host_fifo_watermark.19075511736129312189872390129557469330569504749927056665049184003095843420424
Log /nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_host_fifo_watermark/latest/run.log
Job timed out after 60 minutes
Test i2c_host_fifo_overflow has 1 failures.
0.i2c_host_fifo_overflow.28071482087401588081238345997779706406948158575220339442539689264004693345586
Log /nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_host_fifo_overflow/latest/run.log
Job timed out after 60 minutes
Test i2c_host_fifo_fmt_empty has 1 failures.
0.i2c_host_fifo_fmt_empty.91250422877590894632432012456374455304223714979663638988243814107566364207307
Log /nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_host_fifo_fmt_empty/latest/run.log
Job timed out after 60 minutes
Test i2c_host_fifo_full has 1 failures.
0.i2c_host_fifo_full.10860262051810857596979092189224631888627957042289586704410677528081236403541
Log /nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_host_fifo_full/latest/run.log
Job timed out after 60 minutes
... and 10 more tests.
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 1 failures:
0.i2c_host_error_intr.38806580153995095490870520756065906283225350690520910828798997452383400221651
Line 89, in log /nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_host_error_intr/latest/run.log
UVM_ERROR @ 15070593 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 15070593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:
0.i2c_target_glitch.86325710471886207649284365475452563767676925571080859292958407259579191363256
Line 90, in log /nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_target_glitch/latest/run.log
UVM_ERROR @ 2068886589 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
UVM_INFO @ 2068886589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:
0.i2c_target_unexp_stop.87560741554926261859104882148465724313536403941280194880045718458047042493372
Line 84, in log /nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 67284224 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 34 [0x22])
UVM_INFO @ 67284224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:
0.i2c_target_hrst.49930731213299739167095053196282521778943057869595460192301370109852280486929
Line 85, in log /nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10393594233 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10393594233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:946) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
0.i2c_target_stress_all_with_rand_reset.52825741440771113916389708950974367316232632213856937604409721167936854787189
Line 93, in log /nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1405413259 ps: (cip_base_vseq.sv:946) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1405413259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:629) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 1 failures:
0.i2c_host_mode_toggle.79381335823375146942932893591592361069653495614720435010809364804176672986626
Line 93, in log /nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 78721381 ps: (i2c_scoreboard.sv:629) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------