KMAC/MASKED Simulation Results

Friday September 12 2025 11:15:38 UTC

GitHub Revision: a99e70f

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke kmac_smoke 45.000s 877.120us 0 1 0.00
V1 csr_hw_reset kmac_csr_hw_reset 4.000s 54.147us 0 1 0.00
V1 csr_rw kmac_csr_rw 4.000s 24.700us 0 1 0.00
V1 csr_bit_bash kmac_csr_bit_bash 12.000s 625.621us 0 1 0.00
V1 csr_aliasing kmac_csr_aliasing 13.000s 1.591ms 0 1 0.00
V1 csr_mem_rw_with_rand_reset kmac_csr_mem_rw_with_rand_reset 5.000s 28.736us 0 1 0.00
V1 regwen_csr_and_corresponding_lockable_csr kmac_csr_rw 4.000s 24.700us 0 1 0.00
kmac_csr_aliasing 13.000s 1.591ms 0 1 0.00
V1 mem_walk kmac_mem_walk 3.000s 22.570us 0 1 0.00
V1 mem_partial_access kmac_mem_partial_access 3.000s 51.368us 0 1 0.00
V1 TOTAL 0 8 0.00
V2 long_msg_and_output kmac_long_msg_and_output 31.050m 52.884ms 0 1 0.00
V2 burst_write kmac_burst_write 10.850m 14.011ms 0 1 0.00
V2 test_vectors kmac_test_vectors_sha3_224 1.002h 372.555ms 0 1 0.00
kmac_test_vectors_sha3_256 50.833m 177.647ms 0 1 0.00
kmac_test_vectors_sha3_384 42.000s 5.391ms 0 1 0.00
kmac_test_vectors_sha3_512 36.000s 1.145ms 0 1 0.00
kmac_test_vectors_shake_128 7.083m 25.770ms 0 1 0.00
kmac_test_vectors_shake_256 9.817m 22.408ms 0 1 0.00
kmac_test_vectors_kmac 6.000s 55.073us 0 1 0.00
kmac_test_vectors_kmac_xof 6.000s 90.144us 0 1 0.00
V2 sideload kmac_sideload 7.950m 20.696ms 0 1 0.00
V2 app kmac_app 5.433m 11.932ms 0 1 0.00
V2 app_with_partial_data kmac_app_with_partial_data 6.733m 11.040ms 0 1 0.00
V2 entropy_refresh kmac_entropy_refresh 7.667m 52.813ms 0 1 0.00
V2 error kmac_error 6.850m 38.173ms 0 1 0.00
V2 key_error kmac_key_error 17.000s 845.907us 0 1 0.00
V2 sideload_invalid kmac_sideload_invalid 12.000s 115.240us 0 1 0.00
V2 edn_timeout_error kmac_edn_timeout_error 3.000s 0 1 0.00
V2 entropy_mode_error kmac_entropy_mode_error 3.000s 0 1 0.00
V2 entropy_ready_error kmac_entropy_ready_error 49.000s 2.768ms 0 1 0.00
V2 lc_escalation kmac_lc_escalation 5.000s 511.282us 0 1 0.00
V2 stress_all kmac_stress_all 20.800m 12.964ms 0 1 0.00
V2 intr_test kmac_intr_test 3.000s 29.863us 0 1 0.00
V2 alert_test kmac_alert_test 4.000s 44.593us 0 1 0.00
V2 tl_d_oob_addr_access kmac_tl_errors 5.000s 271.471us 0 1 0.00
V2 tl_d_illegal_access kmac_tl_errors 5.000s 271.471us 0 1 0.00
V2 tl_d_outstanding_access kmac_csr_hw_reset 4.000s 54.147us 0 1 0.00
kmac_csr_rw 4.000s 24.700us 0 1 0.00
kmac_csr_aliasing 13.000s 1.591ms 0 1 0.00
kmac_same_csr_outstanding 6.000s 161.694us 0 1 0.00
V2 tl_d_partial_access kmac_csr_hw_reset 4.000s 54.147us 0 1 0.00
kmac_csr_rw 4.000s 24.700us 0 1 0.00
kmac_csr_aliasing 13.000s 1.591ms 0 1 0.00
kmac_same_csr_outstanding 6.000s 161.694us 0 1 0.00
V2 TOTAL 0 26 0.00
V2S shadow_reg_update_error kmac_shadow_reg_errors 4.000s 50.417us 0 1 0.00
V2S shadow_reg_read_clear_staged_value kmac_shadow_reg_errors 4.000s 50.417us 0 1 0.00
V2S shadow_reg_storage_error kmac_shadow_reg_errors 4.000s 50.417us 0 1 0.00
V2S shadowed_reset_glitch kmac_shadow_reg_errors 4.000s 50.417us 0 1 0.00
V2S shadow_reg_update_error_with_csr_rw kmac_shadow_reg_errors_with_csr_rw 7.000s 340.565us 0 1 0.00
V2S tl_intg_err kmac_sec_cm 1.850m 3.721ms 0 1 0.00
kmac_tl_intg_err 5.000s 61.915us 0 1 0.00
V2S sec_cm_bus_integrity kmac_tl_intg_err 5.000s 61.915us 0 1 0.00
V2S sec_cm_lc_escalate_en_intersig_mubi kmac_lc_escalation 5.000s 511.282us 0 1 0.00
V2S sec_cm_sw_key_key_masking kmac_smoke 45.000s 877.120us 0 1 0.00
V2S sec_cm_key_sideload kmac_sideload 7.950m 20.696ms 0 1 0.00
V2S sec_cm_cfg_shadowed_config_shadow kmac_shadow_reg_errors 4.000s 50.417us 0 1 0.00
V2S sec_cm_fsm_sparse kmac_sec_cm 1.850m 3.721ms 0 1 0.00
V2S sec_cm_ctr_redun kmac_sec_cm 1.850m 3.721ms 0 1 0.00
V2S sec_cm_packer_ctr_redun kmac_sec_cm 1.850m 3.721ms 0 1 0.00
V2S sec_cm_cfg_shadowed_config_regwen kmac_smoke 45.000s 877.120us 0 1 0.00
V2S sec_cm_fsm_global_esc kmac_lc_escalation 5.000s 511.282us 0 1 0.00
V2S sec_cm_fsm_local_esc kmac_sec_cm 1.850m 3.721ms 0 1 0.00
V2S sec_cm_absorbed_ctrl_mubi kmac_mubi 6.383m 45.524ms 0 1 0.00
V2S sec_cm_sw_cmd_ctrl_sparse kmac_smoke 45.000s 877.120us 0 1 0.00
V2S TOTAL 0 5 0.00
V3 stress_all_with_rand_reset kmac_stress_all_with_rand_reset 3.283m 2.694ms 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 0 40 0.00

Failure Buckets