PATTGEN Simulation Results

Friday September 12 2025 11:15:38 UTC

GitHub Revision: a99e70f

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	3.000s	886.528us	1	1	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	10.000s	25.791us	1	1	100.00
V1	csr_rw	pattgen_csr_rw	20.000s	14.825us	1	1	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	12.000s	763.804us	1	1	100.00
V1	csr_aliasing	pattgen_csr_aliasing	10.000s	59.964us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	10.000s	23.684us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	20.000s	14.825us	1	1	100.00
		pattgen_csr_aliasing	10.000s	59.964us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	perf	pattgen_perf	1.650m	2.635ms	1	1	100.00
V2	cnt_rollover	cnt_rollover	19.000s	13.227ms	1	1	100.00
V2	error	pattgen_error	3.000s	124.715us	1	1	100.00
V2	stress_all	pattgen_stress_all	4.917m	89.371ms	0	1	0.00
V2	alert_test	pattgen_alert_test	3.000s	14.325us	1	1	100.00
V2	intr_test	pattgen_intr_test	10.000s	11.827us	1	1	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	11.000s	985.638us	1	1	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	11.000s	985.638us	1	1	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	10.000s	25.791us	1	1	100.00
		pattgen_csr_rw	20.000s	14.825us	1	1	100.00
		pattgen_csr_aliasing	10.000s	59.964us	1	1	100.00
		pattgen_same_csr_outstanding	10.000s	31.301us	1	1	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	10.000s	25.791us	1	1	100.00
		pattgen_csr_rw	20.000s	14.825us	1	1	100.00
		pattgen_csr_aliasing	10.000s	59.964us	1	1	100.00
		pattgen_same_csr_outstanding	10.000s	31.301us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	pattgen_tl_intg_err	10.000s	72.666us	1	1	100.00
		pattgen_sec_cm	3.000s	849.288us	1	1	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	10.000s	72.666us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	2.533m	20.341ms	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	pattgen_inactive_level	45.000s	10.075ms	0	1	0.00
		TOTAL			15	18	83.33

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=27) has 1 failures:

  • Test pattgen_inactive_level has 1 failures.

    • 0.pattgen_inactive_level.44018103397259904382875703473142780392671309300422142599876925763915003901812
      Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_inactive_level/latest/run.log

        UVM_FATAL @ 10074771291 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xd900ebd0, Comparison=CompareOpEq, exp_data=0x0, call_count=27)
        UVM_INFO @ 10074771291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:946) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test pattgen_stress_all_with_rand_reset has 1 failures.

    • 0.pattgen_stress_all_with_rand_reset.94876304514778452184284644701408973856377524559734999323829766236602078608130
      Line 112, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1311281354 ps: (cip_base_vseq.sv:946) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_ERROR @ 1311297120 ps: (cip_base_vseq.sv:850) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 1311297120 ps: (cip_base_vseq.sv:853) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
        Issuing reset for run 1/10
        UVM_INFO @ 1311377120 ps: (cip_base_vseq.sv:874) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
      

• UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: has 1 failures:

  • Test pattgen_stress_all has 1 failures.

    • 0.pattgen_stress_all.87222227549689217781518155710905996741076887985986678891570904836301071001326
      Line 138, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all/latest/run.log

        UVM_ERROR @ 89371308000 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
        ------------------------------------
        Name      Type          Size  Value
        ------------------------------------
        exp_item  pattgen_item  -     @10890