a99e70f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rv_dm_smoke | 57.000s | 11.361ms | 0 | 1 | 0.00 |
| V1 | jtag_dtm_csr_hw_reset | rv_dm_jtag_dtm_csr_hw_reset | 42.000s | 387.917us | 1 | 1 | 100.00 |
| V1 | jtag_dtm_csr_rw | rv_dm_jtag_dtm_csr_rw | 41.000s | 238.608us | 1 | 1 | 100.00 |
| V1 | jtag_dtm_csr_bit_bash | rv_dm_jtag_dtm_csr_bit_bash | 50.000s | 5.927ms | 1 | 1 | 100.00 |
| V1 | jtag_dtm_csr_aliasing | rv_dm_jtag_dtm_csr_aliasing | 50.000s | 1.392ms | 1 | 1 | 100.00 |
| V1 | jtag_dmi_csr_hw_reset | rv_dm_jtag_dmi_csr_hw_reset | 47.000s | 6.728ms | 1 | 1 | 100.00 |
| V1 | jtag_dmi_csr_rw | rv_dm_jtag_dmi_csr_rw | 53.000s | 2.397ms | 1 | 1 | 100.00 |
| V1 | jtag_dmi_csr_bit_bash | rv_dm_jtag_dmi_csr_bit_bash | 1.633m | 69.248ms | 1 | 1 | 100.00 |
| V1 | jtag_dmi_csr_aliasing | rv_dm_jtag_dmi_csr_aliasing | 53.000s | 22.868ms | 1 | 1 | 100.00 |
| V1 | jtag_dmi_cmderr_busy | rv_dm_cmderr_busy | 51.000s | 264.497us | 1 | 1 | 100.00 |
| V1 | jtag_dmi_cmderr_not_supported | rv_dm_cmderr_not_supported | 44.000s | 611.267us | 1 | 1 | 100.00 |
| V1 | cmderr_exception | rv_dm_cmderr_exception | 33.000s | 379.678us | 1 | 1 | 100.00 |
| V1 | mem_tl_access_resuming | rv_dm_mem_tl_access_resuming | 39.000s | 732.706us | 1 | 1 | 100.00 |
| V1 | mem_tl_access_halted | rv_dm_mem_tl_access_halted | 37.000s | 186.187us | 1 | 1 | 100.00 |
| V1 | cmderr_halt_resume | rv_dm_cmderr_halt_resume | 46.000s | 276.815us | 1 | 1 | 100.00 |
| V1 | dataaddr_rw_access | rv_dm_dataaddr_rw_access | 39.000s | 229.252us | 1 | 1 | 100.00 |
| V1 | halt_resume | rv_dm_halt_resume_whereto | 43.000s | 212.709us | 1 | 1 | 100.00 |
| V1 | progbuf_busy | rv_dm_cmderr_busy | 51.000s | 264.497us | 1 | 1 | 100.00 |
| V1 | abstractcmd_status | rv_dm_abstractcmd_status | 39.000s | 169.389us | 1 | 1 | 100.00 |
| V1 | progbuf_read_write_execute | rv_dm_progbuf_read_write_execute | 45.000s | 326.334us | 1 | 1 | 100.00 |
| V1 | progbuf_exception | rv_dm_cmderr_exception | 33.000s | 379.678us | 1 | 1 | 100.00 |
| V1 | rom_read_access | rv_dm_rom_read_access | 36.000s | 117.718us | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | rv_dm_csr_hw_reset | 42.000s | 133.458us | 1 | 1 | 100.00 |
| V1 | csr_rw | rv_dm_csr_rw | 44.000s | 264.443us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | rv_dm_csr_bit_bash | 1.117m | 1.499ms | 1 | 1 | 100.00 |
| V1 | csr_aliasing | rv_dm_csr_aliasing | 1.833m | 8.532ms | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_dm_csr_mem_rw_with_rand_reset | 49.000s | 130.039us | 0 | 1 | 0.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_dm_csr_aliasing | 1.833m | 8.532ms | 1 | 1 | 100.00 |
| rv_dm_csr_rw | 44.000s | 264.443us | 1 | 1 | 100.00 | ||
| V1 | mem_walk | rv_dm_mem_walk | 52.000s | 112.113us | 1 | 1 | 100.00 |
| V1 | mem_partial_access | rv_dm_mem_partial_access | 43.000s | 47.933us | 1 | 1 | 100.00 |
| V1 | TOTAL | 25 | 27 | 92.59 | |||
| V2 | idcode | rv_dm_smoke | 57.000s | 11.361ms | 0 | 1 | 0.00 |
| V2 | jtag_dtm_hard_reset | rv_dm_jtag_dtm_hard_reset | 40.000s | 439.982us | 1 | 1 | 100.00 |
| V2 | jtag_dtm_idle_hint | rv_dm_jtag_dtm_idle_hint | 48.000s | 108.801us | 1 | 1 | 100.00 |
| V2 | jtag_dmi_failed_op | rv_dm_dmi_failed_op | 44.000s | 300.999us | 1 | 1 | 100.00 |
| V2 | jtag_dmi_dm_inactive | rv_dm_jtag_dmi_dm_inactive | 35.000s | 285.048us | 1 | 1 | 100.00 |
| V2 | sba | rv_dm_sba_tl_access | 17.850m | 300.000ms | 0 | 1 | 0.00 |
| rv_dm_delayed_resp_sba_tl_access | 17.933m | 300.000ms | 0 | 1 | 0.00 | ||
| V2 | bad_sba | rv_dm_bad_sba_tl_access | 5.350m | 300.000ms | 0 | 1 | 0.00 |
| V2 | sba_autoincrement | rv_dm_autoincr_sba_tl_access | 15.233m | 300.000ms | 0 | 1 | 0.00 |
| V2 | jtag_dmi_debug_disabled | rv_dm_jtag_dmi_debug_disabled | 43.000s | 670.785us | 1 | 1 | 100.00 |
| V2 | sba_debug_disabled | rv_dm_sba_debug_disabled | 47.000s | 813.386us | 1 | 1 | 100.00 |
| V2 | ndmreset_req | rv_dm_ndmreset_req | 38.000s | 93.693us | 1 | 1 | 100.00 |
| V2 | hart_unavail | rv_dm_hart_unavail | 36.000s | 93.106us | 1 | 1 | 100.00 |
| V2 | tap_ctrl_transitions | rv_dm_tap_fsm | 1.283m | 13.272ms | 0 | 1 | 0.00 |
| rv_dm_tap_fsm_rand_reset | 41.000s | 123.198us | 0 | 1 | 0.00 | ||
| V2 | hartsel_warl | rv_dm_hartsel_warl | 51.000s | 243.996us | 1 | 1 | 100.00 |
| V2 | stress_all | rv_dm_stress_all | 51.000s | 11.618ms | 0 | 1 | 0.00 |
| V2 | alert_test | rv_dm_alert_test | 46.000s | 104.947us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_dm_tl_errors | 41.000s | 67.583us | 0 | 1 | 0.00 |
| V2 | tl_d_illegal_access | rv_dm_tl_errors | 41.000s | 67.583us | 0 | 1 | 0.00 |
| V2 | tl_d_outstanding_access | rv_dm_csr_aliasing | 1.833m | 8.532ms | 1 | 1 | 100.00 |
| rv_dm_csr_hw_reset | 42.000s | 133.458us | 1 | 1 | 100.00 | ||
| rv_dm_csr_rw | 44.000s | 264.443us | 1 | 1 | 100.00 | ||
| rv_dm_same_csr_outstanding | 46.000s | 996.026us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | rv_dm_csr_aliasing | 1.833m | 8.532ms | 1 | 1 | 100.00 |
| rv_dm_csr_hw_reset | 42.000s | 133.458us | 1 | 1 | 100.00 | ||
| rv_dm_csr_rw | 44.000s | 264.443us | 1 | 1 | 100.00 | ||
| rv_dm_same_csr_outstanding | 46.000s | 996.026us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 11 | 19 | 57.89 | |||
| V2S | tl_intg_err | rv_dm_sec_cm | 41.000s | 591.052us | 1 | 1 | 100.00 |
| rv_dm_tl_intg_err | 54.000s | 2.458ms | 1 | 1 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_dm_tl_intg_err | 54.000s | 2.458ms | 1 | 1 | 100.00 |
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | rv_dm_sba_debug_disabled | 47.000s | 813.386us | 1 | 1 | 100.00 |
| rv_dm_debug_disabled | 38.000s | 78.780us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_lc_dft_en_intersig_mubi | rv_dm_sba_debug_disabled | 47.000s | 813.386us | 1 | 1 | 100.00 |
| rv_dm_debug_disabled | 38.000s | 78.780us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | rv_dm_smoke | 57.000s | 11.361ms | 0 | 1 | 0.00 |
| V2S | sec_cm_dm_en_ctrl_lc_gated | rv_dm_buffered_enable | 42.000s | 305.436us | 1 | 1 | 100.00 |
| V2S | sec_cm_sba_tl_lc_gate_fsm_sparse | rv_dm_sparse_lc_gate_fsm | 54.000s | 122.834us | 1 | 1 | 100.00 |
| V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | rv_dm_sparse_lc_gate_fsm | 54.000s | 122.834us | 1 | 1 | 100.00 |
| V2S | sec_cm_exec_ctrl_mubi | rv_dm_buffered_enable | 42.000s | 305.436us | 1 | 1 | 100.00 |
| V2S | TOTAL | 5 | 5 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_dm_stress_all_with_rand_reset | 39.000s | 31.056us | 0 | 1 | 0.00 |
| V3 | TOTAL | 0 | 1 | 0.00 | |||
| Unmapped tests | rv_dm_scanmode | 51.000s | 13.432us | 1 | 1 | 100.00 | |
| TOTAL | 42 | 53 | 79.25 |
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
Test rv_dm_sba_tl_access has 1 failures.
0.rv_dm_sba_tl_access.59749185697070798367494452607976646711637903122410949770401163158637067970459
Line 84, in log /nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_delayed_resp_sba_tl_access has 1 failures.
0.rv_dm_delayed_resp_sba_tl_access.25797639820986942689542706434176598942478871158627033097604787163334045157887
Line 84, in log /nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_delayed_resp_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_bad_sba_tl_access has 1 failures.
0.rv_dm_bad_sba_tl_access.14995942086635620389777814233260574997486700630244854829509718825921684753848
Line 84, in log /nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_bad_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_autoincr_sba_tl_access has 1 failures.
0.rv_dm_autoincr_sba_tl_access.103440027855901426786681605278903991715900744398650188494181303099047083076310
Line 84, in log /nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,TRNULLID: NULL pointer dereference. has 3 failures:
Test rv_dm_smoke has 1 failures.
0.rv_dm_smoke.12458685648690441474889469112539475441038137921175563763417763292759384371407
Line 97, in log /nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_smoke/latest/run.log
xmsim: *E,TRNULLID: NULL pointer dereference.
File: /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_cip_lib_0/seq_lib/cip_base_vseq.sv, line = 290, pos = 15
Scope: worklib.cip_base_pkg::cip_base_vseq#(rv_dm_regs_ral_pkg::rv_dm_regs_reg_block,rv_dm_env_pkg::rv_dm_env_cfg,rv_dm_env_pkg::rv_dm_env_cov,rv_dm_env_pkg::rv_dm_virtual_sequencer)@23353_169.tl_access_sub
Time: 11360747135 PS + 0
Verilog Stack Trace:
Test rv_dm_tap_fsm has 1 failures.
0.rv_dm_tap_fsm.2976923141210356781363438767441761858338718025227708181367909499449217933847
Line 92, in log /nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_tap_fsm/latest/run.log
xmsim: *E,TRNULLID: NULL pointer dereference.
File: /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_cip_lib_0/seq_lib/cip_base_vseq.sv, line = 290, pos = 15
Scope: worklib.cip_base_pkg::cip_base_vseq#(rv_dm_regs_ral_pkg::rv_dm_regs_reg_block,rv_dm_env_pkg::rv_dm_env_cfg,rv_dm_env_pkg::rv_dm_env_cov,rv_dm_env_pkg::rv_dm_virtual_sequencer)@23794_1.tl_access_sub
Time: 13272097176 PS + 0
Verilog Stack Trace:
Test rv_dm_stress_all has 1 failures.
0.rv_dm_stress_all.36487464716833764774387748397194507390297497859126105903647645761921383592138
Line 90, in log /nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_stress_all/latest/run.log
xmsim: *E,TRNULLID: NULL pointer dereference.
File: /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_cip_lib_0/seq_lib/cip_base_vseq.sv, line = 290, pos = 15
Scope: worklib.cip_base_pkg::cip_base_vseq#(rv_dm_regs_ral_pkg::rv_dm_regs_reg_block,rv_dm_env_pkg::rv_dm_env_cfg,rv_dm_env_pkg::rv_dm_env_cov,rv_dm_env_pkg::rv_dm_virtual_sequencer)@23673_1397.tl_access_sub
Time: 11618273813 PS + 0
Verilog Stack Trace:
UVM_ERROR (cip_base_scoreboard.sv:556) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@25688) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
0.rv_dm_tap_fsm_rand_reset.2806517465646903935227297355528857771190001771369401667174424509228584321730
Line 87, in log /nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 123197705 ps: (cip_base_scoreboard.sv:556) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@25688) { a_addr: 'h3692e7b0 a_data: 'h8f912b20 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h39 a_opcode: 'h4 a_user: 'h1b03a d_param: 'h0 d_source: 'h39 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 123197705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:556) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@24894) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
0.rv_dm_stress_all_with_rand_reset.71770618184701491742293538583981727904695628119911096496360976106314595303481
Line 87, in log /nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 31055553 ps: (cip_base_scoreboard.sv:556) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@24894) { a_addr: 'h2867d63c a_data: 'h1e810710 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'he5 a_opcode: 'h4 a_user: 'h1ab32 d_param: 'h0 d_source: 'he5 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 31055553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:556) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@24713) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
0.rv_dm_tl_errors.15126123922239999322599605713530685968910405357846253229668381413115259526760
Line 86, in log /nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_tl_errors/latest/run.log
UVM_ERROR @ 67582936 ps: (cip_base_scoreboard.sv:556) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@24713) { a_addr: 'h46c8a768 a_data: 'h212e178d a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hce a_opcode: 'h4 a_user: 'h1a9cc d_param: 'h0 d_source: 'hce d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 67582936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:556) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@25541) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
0.rv_dm_csr_mem_rw_with_rand_reset.61778700134363296811849365004014524125977289033348262290307220236302777296343
Line 87, in log /nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 130038666 ps: (cip_base_scoreboard.sv:556) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@25541) { a_addr: 'h583c034c a_data: 'hdeb144ec a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h56 a_opcode: 'h4 a_user: 'h1a717 d_param: 'h0 d_source: 'h56 d_data: 'h13 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd7d a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 130038666 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---