UART Simulation Results

Friday September 12 2025 11:15:38 UTC

GitHub Revision: a99e70f

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	5.000s	453.284us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	3.000s	13.392us	1	1	100.00
V1	csr_rw	uart_csr_rw	3.000s	104.893us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	4.000s	277.283us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	2.000s	223.727us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	3.000s	24.620us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	3.000s	104.893us	1	1	100.00
		uart_csr_aliasing	2.000s	223.727us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	1.633m	33.930ms	1	1	100.00
V2	parity	uart_smoke	5.000s	453.284us	1	1	100.00
		uart_tx_rx	1.633m	33.930ms	1	1	100.00
V2	parity_error	uart_intr	25.000s	10.440ms	1	1	100.00
		uart_rx_parity_err	1.500m	112.441ms	1	1	100.00
V2	watermark	uart_tx_rx	1.633m	33.930ms	1	1	100.00
		uart_intr	25.000s	10.440ms	1	1	100.00
V2	fifo_full	uart_fifo_full	2.200m	88.134ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	1.850m	148.437ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	25.000s	40.966ms	1	1	100.00
V2	rx_frame_err	uart_intr	25.000s	10.440ms	1	1	100.00
V2	rx_break_err	uart_intr	25.000s	10.440ms	1	1	100.00
V2	rx_timeout	uart_intr	25.000s	10.440ms	1	1	100.00
V2	perf	uart_perf	55.000s	25.130ms	1	1	100.00
V2	sys_loopback	uart_loopback	11.000s	3.882ms	1	1	100.00
V2	line_loopback	uart_loopback	11.000s	3.882ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	34.000s	45.652ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.267m	29.442ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	6.000s	1.423ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	5.000s	1.914ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	5.917m	202.177ms	1	1	100.00
V2	stress_all	uart_stress_all	5.200m	498.757ms	1	1	100.00
V2	alert_test	uart_alert_test	3.000s	45.080us	1	1	100.00
V2	intr_test	uart_intr_test	3.000s	33.877us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	4.000s	23.933us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	4.000s	23.933us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	3.000s	13.392us	1	1	100.00
		uart_csr_rw	3.000s	104.893us	1	1	100.00
		uart_csr_aliasing	2.000s	223.727us	1	1	100.00
		uart_same_csr_outstanding	3.000s	43.908us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	3.000s	13.392us	1	1	100.00
		uart_csr_rw	3.000s	104.893us	1	1	100.00
		uart_csr_aliasing	2.000s	223.727us	1	1	100.00
		uart_same_csr_outstanding	3.000s	43.908us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	3.000s	286.158us	1	1	100.00
		uart_tl_intg_err	3.000s	90.537us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	3.000s	90.537us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	19.000s	5.630ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00