CHIP Simulation Results

Friday September 12 2025 11:15:38 UTC

GitHub Revision: a99e70f

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	15.650m	2.716ms	1	1	100.00
		chip_sw_example_rom	7.767m	3.102ms	1	1	100.00
		chip_sw_example_manufacturer	10.350m	2.328ms	1	1	100.00
		chip_sw_example_concurrency	16.467m	3.451ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	8.017m	4.839ms	1	1	100.00
V1	csr_rw	chip_csr_rw	15.700m	4.178ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	24.417m	5.511ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing			0	1	0.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	3.217m	2.676ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing			0	1	0.00
		chip_csr_rw	15.700m	4.178ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	29.000s	46.472us	0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	36.067m	4.403ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	36.067m	4.403ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	36.067m	4.403ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	38.567m	4.000ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	38.567m	4.000ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	36.733m	4.123ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	37.083m	4.376ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	41.167m	4.374ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	1.912h	7.796ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	42.333m	4.510ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed			0	1	0.00
V1		TOTAL			14	18	77.78
V2	chip_pin_mux	chip_padctrl_attributes	16.817m	3.823ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	16.817m	3.823ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	14.250m	2.643ms	0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	11.000m	2.538ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	11.867m	3.392ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	1.409h	9.115ms	1	1	100.00
		chip_tap_straps_testunlock0	45.050m	4.703ms	1	1	100.00
		chip_tap_straps_rma	11.000m	2.910ms	1	1	100.00
		chip_tap_straps_prod	13.450m	2.903ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	19.183m	3.370ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses			0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	48.733m	5.632ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	48.733m	5.632ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs			0	1	0.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs			0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	37.400m	4.506ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en			0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	3.600h	18.968ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	19.950m	3.293ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter			0	1	0.00
		chip_sw_hmac_enc_jitter_en	18.117m	3.104ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en			0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	22.550m	3.660ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	39.233m	5.007ms	1	1	100.00
		chip_sw_clkmgr_jitter	13.400m	2.722ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	21.317m	2.473ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	52.183m	5.300ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	31.050m	5.751ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	18.800m	2.717ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	31.050m	5.751ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	13.450m	2.231ms	1	1	100.00
		chip_sw_aes_smoketest	21.583m	2.952ms	1	1	100.00
		chip_sw_aon_timer_smoketest	16.867m	3.380ms	1	1	100.00
		chip_sw_clkmgr_smoketest	12.500m	3.115ms	1	1	100.00
		chip_sw_csrng_smoketest	12.833m	2.785ms	1	1	100.00
		chip_sw_entropy_src_smoketest			0	1	0.00
		chip_sw_gpio_smoketest	17.683m	3.417ms	1	1	100.00
		chip_sw_hmac_smoketest	19.533m	2.634ms	1	1	100.00
		chip_sw_kmac_smoketest	19.617m	3.446ms	1	1	100.00
		chip_sw_otbn_smoketest			0	1	0.00
		chip_sw_pwrmgr_smoketest	29.317m	6.947ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	27.317m	6.036ms	1	1	100.00
		chip_sw_rv_plic_smoketest	14.350m	2.932ms	1	1	100.00
		chip_sw_rv_timer_smoketest	20.050m	2.680ms	1	1	100.00
		chip_sw_rstmgr_smoketest	14.750m	2.182ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	16.450m	3.043ms	1	1	100.00
		chip_sw_uart_smoketest	19.767m	3.529ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	16.350m	2.921ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	31.517m	4.685ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	7.616h	61.035ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	2.866h	15.009ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	22.950m	6.598ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	24.467m	3.649ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	26.300m	2.860ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap			0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed			0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	3.217m	2.282ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	3.217m	2.282ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing			0	1	0.00
		chip_same_csr_outstanding			0	1	0.00
		chip_csr_hw_reset	8.017m	4.839ms	1	1	100.00
		chip_csr_rw	15.700m	4.178ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing			0	1	0.00
		chip_same_csr_outstanding			0	1	0.00
		chip_csr_hw_reset	8.017m	4.839ms	1	1	100.00
		chip_csr_rw	15.700m	4.178ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	1.767m	1.790ms	0	1	0.00
V2	xbar_random_delay	xbar_smoke_zero_delays	28.000s	42.274us	0	1	0.00
		xbar_smoke_large_delays	1.583m	6.212ms	0	1	0.00
		xbar_smoke_slow_rsp	2.117m	6.302ms	0	1	0.00
		xbar_random_zero_delays	1.433m	491.801us	0	1	0.00
		xbar_random_large_delays	6.950m	38.051ms	0	1	0.00
		xbar_random_slow_rsp	7.683m	27.773ms	0	1	0.00
V2	xbar_unmapped_address	xbar_unmapped_addr	56.000s	501.920us	0	1	0.00
		xbar_error_and_unmapped_addr	27.000s	88.888us	0	1	0.00
V2	xbar_error_cases	xbar_error_random	1.717m	1.850ms	0	1	0.00
		xbar_error_and_unmapped_addr	27.000s	88.888us	0	1	0.00
V2	xbar_all_access_same_device	xbar_access_same_device	2.050m	1.754ms	0	1	0.00
		xbar_access_same_device_slow_rsp	10.450m	41.400ms	0	1	0.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	2.500m	2.613ms	0	1	0.00
V2	xbar_stress_all	xbar_stress_all	4.817m	1.893ms	0	1	0.00
		xbar_stress_all_with_error	3.200m	1.311ms	0	1	0.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	7.250m	777.458us	0	1	0.00
		xbar_stress_all_with_reset_error	1.583m	286.552us	0	1	0.00
V2	rom_e2e_smoke	rom_e2e_smoke	2.866h	15.009ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	1.158h	9.813ms	0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	2.761h	15.319ms	0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	2.223h	11.917ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	2.878h	15.487ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	2.984h	18.687ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	2.924h	16.315ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	2.734h	14.848ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	29.000s	10.400us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	30.000s	10.320us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	29.000s	10.360us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	29.000s	10.140us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	29.000s	10.380us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	29.000s	10.180us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	28.000s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	28.000s	10.240us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	27.000s	10.280us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	29.000s	10.320us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	29.000s	10.120us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	27.000s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	27.000s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	29.000s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	29.000s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	28.000s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	28.000s	10.120us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	28.000s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	26.000s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	26.000s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	30.000s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	26.000s	10.120us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	26.000s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	29.000s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	29.000s	10.380us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	2.069h	11.337ms	1	1	100.00
		rom_e2e_asm_init_dev	2.773h	15.580ms	1	1	100.00
		rom_e2e_asm_init_prod	2.828h	16.874ms	1	1	100.00
		rom_e2e_asm_init_prod_end	2.757h	15.719ms	1	1	100.00
		rom_e2e_asm_init_rma	2.698h	15.350ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	2.685h	15.315ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	2.670h	14.865ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	2.676h	15.274ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	2.746h	15.581ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup			0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup			0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	20.983m	3.207ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	19.950m	3.293ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	14.400m	2.667ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	17.467m	2.667ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes			0	1	0.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	20.217m	3.033ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	46.083m	4.749ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	37.550m	4.809ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0			0	1	0.00
		chip_plic_all_irqs_10	34.617m	3.854ms	1	1	100.00
		chip_plic_all_irqs_20	47.950m	4.395ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	29.817m	3.601ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info			0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	33.883m	3.626ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	14.617m	2.441ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	1.669h	13.302ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	1.858h	8.067ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	1.646h	6.497ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok			0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep			0	1	0.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	31.950m	3.782ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	29.317m	6.947ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	31.950m	3.782ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset			0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset			0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	34.817m	7.685ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	42.300m	4.066ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness			0	1	0.00
		chip_sw_aes_idle	17.467m	2.667ms	1	1	100.00
		chip_sw_hmac_enc_idle	16.733m	2.588ms	1	1	100.00
		chip_sw_kmac_idle	16.617m	2.902ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	28.167m	4.375ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	24.750m	3.486ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	27.367m	4.634ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	31.600m	4.614ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri			0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	43.083m	4.274ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	45.850m	4.869ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	46.133m	4.140ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	43.683m	4.476ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	39.183m	3.799ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	49.150m	5.286ms	1	1	100.00
		chip_sw_ast_clk_outputs			0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	46.650m	6.600ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	46.133m	4.140ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	43.683m	4.476ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	37.400m	4.506ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en			0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	3.600h	18.968ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	19.950m	3.293ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter			0	1	0.00
		chip_sw_hmac_enc_jitter_en	18.117m	3.104ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en			0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	22.550m	3.660ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	39.233m	5.007ms	1	1	100.00
		chip_sw_clkmgr_jitter	13.400m	2.722ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	12.083m	2.927ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	39.133m	4.458ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq			0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	3.238h	24.601ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	17.817m	3.519ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	15.783m	3.041ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq			0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	17.950m	3.046ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	32.983m	4.621ms	1	1	100.00
		chip_sw_flash_init_reduced_freq			0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq			0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs			0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	42.233m	4.657ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	32.967m	3.521ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	37.550m	4.809ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	1.858h	8.067ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	1.665h	7.027ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	38.067m	3.748ms	1	1	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test			0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	16.967m	2.739ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency			0	1	0.00
		chip_sw_entropy_src_ast_rng_req	20.517m	2.924ms	1	1	100.00
		chip_sw_edn_entropy_reqs			0	1	0.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	20.517m	2.924ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	1.665h	7.027ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	14.083m	2.849ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init			0	1	0.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access			0	1	0.00
		chip_sw_flash_ctrl_access_jitter_en			0	1	0.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	32.367m	3.300ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	37.400m	4.506ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked			0	1	0.00
V2	chip_sw_flash_scramble	chip_sw_flash_init			0	1	0.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	26.450m	3.302ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation			0	1	0.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	34.100m	5.324ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked			0	1	0.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	34.100m	5.324ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	34.100m	5.324ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	34.100m	5.324ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	34.100m	5.324ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	37.550m	4.809ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	21.033m	9.638ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	54.983m	4.481ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	52.200m	5.700ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	52.200m	5.700ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	16.033m	2.899ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	18.117m	3.104ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	16.733m	2.588ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	16.783m	2.802ms	0	1	0.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	32.833m	3.786ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	48.633m	5.084ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	46.350m	4.512ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	52.783m	5.514ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	32.167m	3.812ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation			0	1	0.00
		chip_sw_keymgr_key_derivation_jitter_en			0	1	0.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac			0	1	0.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes			0	1	0.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	2.909h	13.467ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	16.967m	2.370ms	1	1	100.00
		chip_sw_kmac_mode_kmac	22.367m	2.919ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	22.550m	3.660ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation			0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition			0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	11.933m	3.068ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy			0	1	0.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	16.617m	2.902ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	46.083m	4.749ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	1.409h	9.115ms	1	1	100.00
		chip_tap_straps_rma	11.000m	2.910ms	1	1	100.00
		chip_tap_straps_prod	13.450m	2.903ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	18.667m	3.497ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition			0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition			0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition			0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod			0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	34.100m	5.324ms	1	1	100.00
		chip_sw_flash_rma_unlocked			0	1	0.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	20.417m	3.156ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	54.017m	5.667ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod			0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	52.133m	5.441ms	1	1	100.00
		chip_sw_lc_ctrl_transition			0	1	0.00
		chip_sw_keymgr_key_derivation			0	1	0.00
		chip_sw_rom_ctrl_integrity_check	50.767m	8.919ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main			0	1	0.00
		chip_prim_tl_access	21.033m	9.638ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	46.650m	6.600ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	43.083m	4.274ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	45.850m	4.869ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	46.133m	4.140ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	43.683m	4.476ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	39.183m	3.799ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	49.150m	5.286ms	1	1	100.00
		chip_tap_straps_dev	1.409h	9.115ms	1	1	100.00
		chip_tap_straps_rma	11.000m	2.910ms	1	1	100.00
		chip_tap_straps_prod	13.450m	2.903ms	1	1	100.00
		chip_rv_dm_lc_disabled	29.800m	13.496ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	16.450m	3.649ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	9.483m	3.429ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	9.417m	3.292ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	10.217m	3.398ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks			0	1	0.00
		chip_rv_dm_lc_disabled	29.800m	13.496ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev			0	1	0.00
		chip_sw_lc_walkthrough_prod			0	1	0.00
		chip_sw_lc_walkthrough_prodend			0	1	0.00
		chip_sw_lc_walkthrough_rma			0	1	0.00
		chip_sw_lc_walkthrough_testunlocks			0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	7.283m	2.874ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	7.233m	2.353ms	1	1	100.00
		rom_volatile_raw_unlock	8.233m	2.960ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	3.559h	17.132ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	3.600h	18.968ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness			0	1	0.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness			0	1	0.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness			0	1	0.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	33.933m	3.733ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition			0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init			0	1	0.00
		chip_sw_otbn_mem_scramble	33.933m	3.733ms	1	1	100.00
		chip_sw_keymgr_key_derivation			0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	40.850m	4.996ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	16.017m	2.777ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init			0	1	0.00
		chip_sw_otbn_mem_scramble	33.933m	3.733ms	1	1	100.00
		chip_sw_keymgr_key_derivation			0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	40.850m	4.996ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	16.017m	2.777ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition			0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	35.017m	4.216ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	18.667m	3.497ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	20.417m	3.156ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	54.017m	5.667ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod			0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	52.133m	5.441ms	1	1	100.00
		chip_sw_lc_ctrl_transition			0	1	0.00
		chip_prim_tl_access	21.033m	9.638ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	21.033m	9.638ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock			0	1	0.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	30.300m	8.845ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups			0	1	0.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	26.100m	6.904ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	41.233m	8.744ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset			0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups			0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs			0	1	0.00
		chip_sw_aon_timer_wdog_bite_reset			0	1	0.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	1.634h	12.609ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	41.067m	4.859ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	30.300m	8.845ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	11.733m	2.913ms	0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset			0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	17.067m	2.797ms	0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	15.050m	3.082ms	0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs			0	1	0.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset			0	1	0.00
		chip_sw_pwrmgr_all_reset_reqs	1.824h	10.967ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req			0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	14.250m	2.915ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	37.550m	4.809ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	50.767m	8.919ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	50.767m	8.919ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	1.824h	10.967ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs			0	1	0.00
		chip_sw_pwrmgr_wdog_reset	41.067m	4.859ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	29.317m	6.947ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	30.450m	5.189ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	34.100m	4.752ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	26.167m	4.779ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info			0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	14.617m	3.077ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	37.550m	4.809ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	1.646h	6.497ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq			0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	56.467m	4.851ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	18.050m	2.774ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	16.017m	2.777ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	34.100m	4.752ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	34.100m	4.752ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw			0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access			0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	30.450m	5.189ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	33.467m	3.835ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	26.367m	6.373ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	11.000m	2.910ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	29.800m	13.496ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0			0	1	0.00
		chip_plic_all_irqs_10	34.617m	3.854ms	1	1	100.00
		chip_plic_all_irqs_20	47.950m	4.395ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	14.383m	2.800ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	16.000m	3.313ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	2.866h	15.009ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through			0	1	0.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	20.167m	3.282ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	19.933m	3.264ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	14.350m	2.814ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	40.850m	4.996ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	39.233m	5.007ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble			0	1	0.00
		chip_sw_sleep_sram_ret_contents_scramble	42.900m	6.993ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main			0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	37.550m	4.809ms	1	1	100.00
		chip_sw_data_integrity_escalation	48.733m	5.632ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset			0	1	0.00
		chip_sw_sysrst_ctrl_reset			0	1	0.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	11.933m	2.807ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	25.667m	3.836ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	48.450m	4.499ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset			0	1	0.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset			0	1	0.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l			0	1	0.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l			0	1	0.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	30.650m	5.331ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup			0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	16.267m	3.077ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	16.117m	3.204ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	26.417m	3.954ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	33.600m	3.696ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host			0	1	0.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg			0	1	0.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi			0	1	0.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	17.067m	2.806ms	1	1	100.00
V2		TOTAL			158	275	57.45
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	19.450m	3.405ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	16.683m	3.482ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_sw_coremark	chip_sw_coremark			0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	1.233h	5.733ms	1	1	100.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	1.659h	11.414ms	1	1	100.00
		rom_e2e_jtag_debug_dev	1.113h	14.498ms	0	1	0.00
		rom_e2e_jtag_debug_rma	54.967m	14.338ms	0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	19.900m	3.530ms	1	1	100.00
		rom_e2e_jtag_inject_dev	24.950m	4.451ms	1	1	100.00
		rom_e2e_jtag_inject_rma	21.200m	4.475ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	40.982s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency			0	1	0.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	35.067m	2.665ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	1.041h	4.143ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode			0	1	0.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	25.367m	2.087ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	51.100m	4.701ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	6.250m	2.404ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	43.733m	5.756ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	35.317m	5.591ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	30.800m	4.725ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	1.824h	10.967ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	1.659h	11.414ms	1	1	100.00
		rom_e2e_jtag_debug_dev	1.113h	14.498ms	0	1	0.00
		rom_e2e_jtag_debug_rma	54.967m	14.338ms	0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	38.467m	4.625ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	37.550m	4.809ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test			0	1	0.00
V3	counter_wrap	chip_sw_rv_timer_systick_test			0	1	0.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	12.900m	3.367ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	38.567m	4.000ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream			0	1	0.00
V3		TOTAL			15	23	65.22
	Unmapped tests	chip_sival_flash_info_access	17.317m	3.627ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	38.700m	4.948ms	1	1	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	13.500m	2.674ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	16.067m	2.728ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	26.800m	3.504ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	20.460s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	23.033m	3.343ms	1	1	100.00
		TOTAL			195	325	60.00

Failure Buckets

• Job timed out after * minutes has 68 failures:

  • Test chip_csr_aliasing has 1 failures.

    • 0.chip_csr_aliasing.100424807142171450417621225035655788575562471261187795825537328145504045727880
      Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_csr_aliasing/latest/run.log

        Job timed out after 180 minutes
      

  • Test chip_same_csr_outstanding has 1 failures.

    • 0.chip_same_csr_outstanding.88812741520783711899074304401586355773357996394197235946131070479155889454570
      Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_same_csr_outstanding/latest/run.log

        Job timed out after 120 minutes
      

  • Test chip_sw_sleep_pwm_pulses has 1 failures.

    • 0.chip_sw_sleep_pwm_pulses.66959890652200046047450170755243293067513920513544223941742297887365190721986
      Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_sw_sleep_pwm_pulses/latest/run.log

        Job timed out after 60 minutes
      

  • Test chip_sw_usbdev_dpi has 1 failures.

    • 0.chip_sw_usbdev_dpi.7907516909627595421804064720647235049792828917739101957617997606673556626129
      Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_sw_usbdev_dpi/latest/run.log

        Job timed out after 120 minutes
      

  • Test chip_sw_usbdev_config_host has 1 failures.

    • 0.chip_sw_usbdev_config_host.102524016291965794534085101985877090469024211706491737857608029163619317697093
      Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_sw_usbdev_config_host/latest/run.log

        Job timed out after 60 minutes
      

  • ... and 63 more tests.

• xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_*/xbar_env_cov.sv:25) with 'rv_core_ibex__cored' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_*/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__cored' in the same scope was earlier saved to the database. has 18 failures:

  • Test xbar_smoke has 1 failures.

    • 0.xbar_smoke.47985391233977870818876540928218651513964514074959005212338197553842347609368
      Line 248, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.xbar_smoke/latest/run.log

        xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__cored' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__cored' in the same scope was earlier saved to the database.
        xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__corei' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__corei' in the same scope was earlier saved to the database.
        xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_dm__sba' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_dm__sba' in the same scope was earlier saved to the database.
        xmsim: *W,COVNBT: (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:282): Name of named block scope "gen_h2d" shall not be suffixed with a redundant "_T" in IMC type-based coverage in subsequent release in default mode. There may be other such named block scopes in the design.
      

  • Test xbar_smoke_zero_delays has 1 failures.

    • 0.xbar_smoke_zero_delays.10566346989477260669056654128317997388088181264222772652887988340261530687118
      Line 248, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.xbar_smoke_zero_delays/latest/run.log

        xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__cored' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__cored' in the same scope was earlier saved to the database.
        xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__corei' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__corei' in the same scope was earlier saved to the database.
        xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_dm__sba' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_dm__sba' in the same scope was earlier saved to the database.
        xmsim: *W,COVNBT: (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:282): Name of named block scope "gen_h2d" shall not be suffixed with a redundant "_T" in IMC type-based coverage in subsequent release in default mode. There may be other such named block scopes in the design.
      

  • Test xbar_smoke_large_delays has 1 failures.

    • 0.xbar_smoke_large_delays.107399468116826711857408815383769279183215423854288972206140575118925510864065
      Line 248, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.xbar_smoke_large_delays/latest/run.log

        xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__cored' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__cored' in the same scope was earlier saved to the database.
        xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__corei' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__corei' in the same scope was earlier saved to the database.
        xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_dm__sba' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_dm__sba' in the same scope was earlier saved to the database.
        xmsim: *W,COVNBT: (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:282): Name of named block scope "gen_h2d" shall not be suffixed with a redundant "_T" in IMC type-based coverage in subsequent release in default mode. There may be other such named block scopes in the design.
      

  • Test xbar_smoke_slow_rsp has 1 failures.

    • 0.xbar_smoke_slow_rsp.23004605597179160089091355899504650687131359974525248496127952846146542965556
      Line 248, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.xbar_smoke_slow_rsp/latest/run.log

        xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__cored' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__cored' in the same scope was earlier saved to the database.
        xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__corei' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__corei' in the same scope was earlier saved to the database.
        xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_dm__sba' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_dm__sba' in the same scope was earlier saved to the database.
        xmsim: *W,COVNBT: (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:282): Name of named block scope "gen_h2d" shall not be suffixed with a redundant "_T" in IMC type-based coverage in subsequent release in default mode. There may be other such named block scopes in the design.
      

  • Test xbar_random has 1 failures.

    • 0.xbar_random.100364258047466725382456158791686163770451918899437308650531635688940362450218
      Line 305, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.xbar_random/latest/run.log

        xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__cored' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__cored' in the same scope was earlier saved to the database.
        xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__corei' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__corei' in the same scope was earlier saved to the database.
        xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_dm__sba' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_dm__sba' in the same scope was earlier saved to the database.
        xmsim: *W,COVNBT: (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:282): Name of named block scope "gen_h2d" shall not be suffixed with a redundant "_T" in IMC type-based coverage in subsequent release in default mode. There may be other such named block scopes in the design.
      

  • ... and 13 more tests.

• UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:

  • Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.

    • 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.109757253871284027647464256548801334556076773061788511052075498940845747533130
      Line 580, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log

        UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
        UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.

    • 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.109350025771094283260223860609498775813354901590538340945167184468144004823661
      Line 634, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log

        UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
        UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.

    • 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.55653726931359294255982199069637386128479247506874660163155275352269256509409
      Line 671, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log

        UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
        UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.

    • 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.66153958581011362386160187890622692333219131692875550434045871638437917337795
      Line 820, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log

        UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
        UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.

    • 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.70295284871183407152519975671342510241692418082867820881278750281177937557420
      Line 682, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log

        UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
        UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • ... and 6 more tests.

• UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:

  • Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.

    • 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.19716132457774068704796802551692129161958249180753292278037441528350178681010
      Line 573, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log

        UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
        UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.

    • 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.88351342210345181508834815088671295228131473213406835590390310714115805136972
      Line 579, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log

        UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
        UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.

    • 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.97196563959454818920641754439551263094692995361085832508794070243067742524206
      Line 579, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log

        UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
        UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.

    • 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.95899007756792404090968359637138720832709319155958343811041027810260444500600
      Line 539, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log

        UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
        UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.

    • 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.1246505220607894348586932231453325748157244135896007247958613358650491404039
      Line 536, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log

        UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
        UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:

  • Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.

    • 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.105044637555974552471704066737832734609577096914495493512966927702581328824641
      Line 665, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log

        UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
        UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.

    • 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.103948891591459474979302338962223244647262309920568136791378920594153474803047
      Line 757, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log

        UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
        UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.

    • 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.49384591147073439743730156616302668682119681463933862966795577087566000453683
      Line 762, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log

        UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
        UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• xmsim: *E,ASRTST (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_earlgrey_ip_pwrmgr_*/rtl/pwrmgr_slow_fsm.sv,362): Assertion IntRstReq_A has failed has 2 failures:

  • Test chip_sw_pwrmgr_main_power_glitch_reset has 1 failures.

    • 0.chip_sw_pwrmgr_main_power_glitch_reset.105683257546104483677031294650808651901961760325547897207405605484993788381861
      Line 396, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_sw_pwrmgr_main_power_glitch_reset/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_earlgrey_ip_pwrmgr_0.1/rtl/pwrmgr_slow_fsm.sv,362): (time 2912660500 PS) Assertion tb.dut.top_earlgrey.u_pwrmgr_aon.u_slow_fsm.IntRstReq_A has failed
        UVM_ERROR @ 2912.660500 us: (pwrmgr_slow_fsm.sv:362) [ASSERT FAILED] IntRstReq_A
        UVM_INFO @ 2912.660500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test chip_sw_pwrmgr_deep_sleep_power_glitch_reset has 1 failures.

    • 0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.43973199927820454777199617063945208409940259474658834386159992132485038018733
      Line 408, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_earlgrey_ip_pwrmgr_0.1/rtl/pwrmgr_slow_fsm.sv,362): (time 2797235500 PS) Assertion tb.dut.top_earlgrey.u_pwrmgr_aon.u_slow_fsm.IntRstReq_A has failed
        UVM_ERROR @ 2797.235500 us: (pwrmgr_slow_fsm.sv:362) [ASSERT FAILED] IntRstReq_A
        UVM_INFO @ 2797.235500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job returned non-zero exit code has 2 failures:

  • Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

    • 0.chip_sw_pwrmgr_sleep_wake_5_bug.102369985252545902436223210558342528748960530249253477299954778621797520102096
      Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

        Computing main repo mapping:
        Loading:
        Loading: 0 packages loaded
        WARNING: Target pattern parsing failed.
        ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
        ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
        INFO: Elapsed time: 1.016s
        INFO: 0 processes.
        ERROR: Build did NOT complete successfully
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

  • Test rom_e2e_self_hash has 1 failures.

    • 0.rom_e2e_self_hash.65865741631371564680479344820204476926265545222781207392898240010179096415326
      Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_self_hash/latest/run.log

        Computing main repo mapping:
        Loading:
        Loading: 0 packages loaded
        WARNING: Target pattern parsing failed.
        ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
        ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
        INFO: Elapsed time: 26.736s
        INFO: 0 processes.
        ERROR: Build did NOT complete successfully
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

• UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:

  • Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.

    • 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.13238411943587316015966840555362921750958405055138476488257651477324321981860
      Line 665, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log

        UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
        UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.

    • 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.8365017442768447767543366965231422165181082563486494663990578055921354895469
      Line 570, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log

        UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
        UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:

  • Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.

    • 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.24822177042208560320656599551782008417981801494297505464849581489213398835787
      Line 857, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log

        UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
        UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.

    • 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.98550783934395803949812770081061994494636390288854343691607954463981475233711
      Line 524, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log

        UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
        UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL @ * us: (jtag_rv_debugger.sv:117) [debugger] timeout occurred! has 2 failures:

  • Test rom_e2e_jtag_debug_dev has 1 failures.

    • 0.rom_e2e_jtag_debug_dev.52443769747348214432977882118832582824937869059264028610161392175868492926440
      Line 498, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_jtag_debug_dev/latest/run.log

        UVM_FATAL @ 14498.379545 us: (jtag_rv_debugger.sv:117) [debugger] timeout occurred!
        UVM_INFO @ 14498.379545 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_e2e_jtag_debug_rma has 1 failures.

    • 0.rom_e2e_jtag_debug_rma.84853620693379180568769214180040358692685504647355516067796038908699239765994
      Line 564, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_jtag_debug_rma/latest/run.log

        UVM_FATAL @ 14338.084462 us: (jtag_rv_debugger.sv:117) [debugger] timeout occurred!
        UVM_INFO @ 14338.084462 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [*] vs *xz [z]) for MIO[*] has 1 failures:

  • Test chip_sw_sleep_pin_mio_dio_val has 1 failures.

    • 0.chip_sw_sleep_pin_mio_dio_val.109055311656923495658771828818030491575659431204569197093956451185487854331447
      Line 642, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_sw_sleep_pin_mio_dio_val/latest/run.log

        UVM_ERROR @ 2642.565000 us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (0x0 [0] vs 0xz [z]) for MIO[30]
        UVM_INFO @ 2642.565000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:

  • Test chip_sw_spi_device_pass_through_collision has 1 failures.

    • 0.chip_sw_spi_device_pass_through_collision.58554807597252808269037981160100253861726830304873304948749128990194145085091
      Line 401, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_sw_spi_device_pass_through_collision/latest/run.log

        UVM_ERROR @ 3281.840920 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
        UVM_INFO @ 3281.840920 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (cip_base_scoreboard.sv:556) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@175397) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

  • Test chip_sw_rstmgr_cpu_info has 1 failures.

    • 0.chip_sw_rstmgr_cpu_info.79630120957223691851043178563373590629887467610844571592506721550202277905132
      Line 420, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_sw_rstmgr_cpu_info/latest/run.log

        UVM_ERROR @ 4751.750640 us: (cip_base_scoreboard.sv:556) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@175397) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
        , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
        UVM_INFO @ 4751.750640 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• xmsim: *E,ASRTST (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_earlgrey_ip_pwrmgr_*/rtl/pwrmgr_slow_fsm.sv,362): (time * NS) Assertion IntRstReq_A has failed has 1 failures:

  • Test chip_sw_pwrmgr_sleep_power_glitch_reset has 1 failures.

    • 0.chip_sw_pwrmgr_sleep_power_glitch_reset.109143090381258951998784332261616004258527763668074981999250525415075892758075
      Line 408, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_sw_pwrmgr_sleep_power_glitch_reset/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_earlgrey_ip_pwrmgr_0.1/rtl/pwrmgr_slow_fsm.sv,362): (time 3081766 NS) Assertion tb.dut.top_earlgrey.u_pwrmgr_aon.u_slow_fsm.IntRstReq_A has failed
        UVM_ERROR @ 3081.766000 us: (pwrmgr_slow_fsm.sv:362) [ASSERT FAILED] IntRstReq_A
        UVM_INFO @ 3081.766000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:

  • Test chip_sw_alert_test has 1 failures.

    • 0.chip_sw_alert_test.67016166896963157425055982436628033417204615792015959605609505090821169394280
      Line 442, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_sw_alert_test/latest/run.log

        UVM_ERROR @ 3033.496088 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
        UVM_INFO @ 3033.496088 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:

  • Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.

    • 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.99188733318653918591956579805661177100607003321441129338721436116852026960854
      Line 510, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log

        UVM_ERROR @ 2440.881730 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
        UVM_INFO @ 2440.881730 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: *. has 1 failures:

  • Test chip_sw_hmac_oneshot has 1 failures.

    • 0.chip_sw_hmac_oneshot.803490921173058321537963428540752414429439515453007039106170938385946933668
      Line 394, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_sw_hmac_oneshot/latest/run.log

        UVM_ERROR @ 2801.937685 us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: 8000534a.
        UVM_INFO @ 2801.937685 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (cip_base_scoreboard.sv:556) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@176167) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

  • Test chip_tl_errors has 1 failures.

    • 0.chip_tl_errors.26092140560237398457498014284747107162195331913298761963771209325623604400487
      Line 207, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_tl_errors/latest/run.log

        UVM_ERROR @ 2282.276176 us: (cip_base_scoreboard.sv:556) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@176167) { a_addr: 'h104f0  a_data: 'h6b6a0298  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1f  a_opcode: 'h4  a_user: 'h1b1c1  d_param: 'h0  d_source: 'h1f  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
        , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
        UVM_INFO @ 2282.276176 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:92) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:

  • Test chip_sw_power_idle_load has 1 failures.

    • 0.chip_sw_power_idle_load.27498822989504758992682562850432709383105524325700495117234541211682932148739
      Line 393, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_sw_power_idle_load/latest/run.log

        UVM_ERROR @ 3648.967500 us: (chip_sw_power_idle_load_vseq.sv:92) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH0 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
        UVM_INFO @ 3648.967500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:115) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:

  • Test chip_sw_power_sleep_load has 1 failures.

    • 0.chip_sw_power_sleep_load.47348577523913056567021631570352282785125672904244685181064084459017002480571
      Line 399, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_sw_power_sleep_load/latest/run.log

        UVM_ERROR @ 2860.129000 us: (chip_sw_power_sleep_load_vseq.sv:115) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH0 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
        UVM_INFO @ 2860.129000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:37) [chip_sw_rom_e2e_shutdown_exception_c_vseq] Check failed "OpenTitan:*-*-* has 1 failures:

  • Test rom_e2e_shutdown_exception_c has 1 failures.

    • 0.rom_e2e_shutdown_exception_c.114619342481997226611688663794609332771484338767664732257597316780392481881745
      Line 449, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_shutdown_exception_c/latest/run.log

        UVM_ERROR @ 15319.077975 us: (chip_sw_rom_e2e_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_shutdown_exception_c_vseq] Check failed "OpenTitan:4001-0002-01
        BF" == "OpenTitan:4001-0002-01x0d
        "
        UVM_INFO @ 15319.077975 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:37) [chip_sw_rom_e2e_shutdown_output_vseq] Check failed "OpenTitan:*-*-* has 1 failures:

  • Test rom_e2e_shutdown_output has 1 failures.

    • 0.rom_e2e_shutdown_output.8449155166942206603734083816938304686944215678787534680214348037712412806309
      Line 453, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_shutdown_output/latest/run.log

        UVM_ERROR @ 9812.710818 us: (chip_sw_rom_e2e_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_shutdown_output_vseq] Check failed "OpenTitan:4001-0002-01
        BF" == "OpenTitan:4001-0002-01x0d
        "
        UVM_INFO @ 9812.710818 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:

  • Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.

    • 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.88912671636869621173901038621147889606263326020524985741555750817949526192647
      Line 831, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log

        UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
        UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:

  • Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.

    • 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.97742319561793086261830163878060917100603852602275118424132897880262124027835
      Line 699, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log

        UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
        UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (cip_base_scoreboard.sv:556) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@176254) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

  • Test chip_csr_mem_rw_with_rand_reset has 1 failures.

    • 0.chip_csr_mem_rw_with_rand_reset.82514201652571538782393718616344197676423883675063380858930767670455314112256
      Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @ 2676.140768 us: (cip_base_scoreboard.sv:556) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@176254) { a_addr: 'h10508  a_data: 'h393b1eab  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h4  a_user: 'h18673  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
        , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
        UVM_INFO @ 2676.140768 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---