ADC_CTRL Simulation Results

Monday September 15 2025 00:04:07 UTC

GitHub Revision: c127aed

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	7.000s	6.051ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	5.000s	1.306ms	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	4.000s	316.735us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	12.000s	2.605ms	0	1	0.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	8.000s	884.754us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	4.000s	603.815us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	4.000s	316.735us	1	1	100.00
		adc_ctrl_csr_aliasing	8.000s	884.754us	1	1	100.00
V1		TOTAL			5	6	83.33
V2	filters_polled	adc_ctrl_filters_polled	4.767m	166.547ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	4.517m	321.898ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	7.933m	487.080ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	9.000m	497.696ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	12.183m	391.976ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	9.100m	598.088ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	2.217m	178.616ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	28.783m	2.000s	0	1	0.00
V2	poweron_counter	adc_ctrl_poweron_counter	7.000s	3.777ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	47.000s	23.269ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	2.000s	446.150us	0	1	0.00
V2	stress_all	adc_ctrl_stress_all	6.000s	830.725us	0	1	0.00
V2	alert_test	adc_ctrl_alert_test	4.000s	435.194us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	5.000s	473.490us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	6.000s	554.283us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	6.000s	554.283us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	5.000s	1.306ms	1	1	100.00
		adc_ctrl_csr_rw	4.000s	316.735us	1	1	100.00
		adc_ctrl_csr_aliasing	8.000s	884.754us	1	1	100.00
		adc_ctrl_same_csr_outstanding	10.000s	2.222ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	5.000s	1.306ms	1	1	100.00
		adc_ctrl_csr_rw	4.000s	316.735us	1	1	100.00
		adc_ctrl_csr_aliasing	8.000s	884.754us	1	1	100.00
		adc_ctrl_same_csr_outstanding	10.000s	2.222ms	1	1	100.00
V2		TOTAL			13	16	81.25
V2S	tl_intg_err	adc_ctrl_sec_cm	31.000s	7.633ms	1	1	100.00
		adc_ctrl_tl_intg_err	12.000s	4.143ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	12.000s	4.143ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	8.000s	6.408ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	25	84.00

Failure Buckets

• xmsim: *E,ASRTST (/nightly/current_run/scratch/master/adc_ctrl-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_adc_ctrl_*/rtl/adc_ctrl_fsm.sv,385): Assertion NpCntClrPwrDn_A has failed has 2 failures:

  • Test adc_ctrl_fsm_reset has 1 failures.

    • 0.adc_ctrl_fsm_reset.5802187006388875560037982002900053749277783465166127452141396000431867185415
      Line 166, in log /nightly/current_run/scratch/master/adc_ctrl-sim-xcelium/0.adc_ctrl_fsm_reset/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/adc_ctrl-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_fsm.sv,385): (time 446150419 PS) Assertion tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.NpCntClrPwrDn_A has failed
        UVM_ERROR @ 446150419 ps: (adc_ctrl_fsm.sv:385) [ASSERT FAILED] NpCntClrPwrDn_A
        UVM_INFO @ 446150419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test adc_ctrl_stress_all has 1 failures.

    • 0.adc_ctrl_stress_all.57594419339736082467223718417324653183036976913248147621470492016121846774592
      Line 167, in log /nightly/current_run/scratch/master/adc_ctrl-sim-xcelium/0.adc_ctrl_stress_all/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/adc_ctrl-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_fsm.sv,385): (time 830724904 PS) Assertion tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.NpCntClrPwrDn_A has failed
        UVM_ERROR @ 830724904 ps: (adc_ctrl_fsm.sv:385) [ASSERT FAILED] NpCntClrPwrDn_A
        UVM_INFO @ 830724904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test adc_ctrl_clock_gating has 1 failures.

    • 0.adc_ctrl_clock_gating.36101981719405079275460567713937750297234622204138789567866853815905778374526
      Line 162, in log /nightly/current_run/scratch/master/adc_ctrl-sim-xcelium/0.adc_ctrl_clock_gating/latest/run.log

        UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• xmsim: *E,ASRTST (/nightly/current_run/scratch/master/adc_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_ip_adc_ctrl_*/rtl/adc_ctrl_fsm.sv,382): Assertion LpSampleCntCfg_M has failed has 1 failures:

  • Test adc_ctrl_csr_bit_bash has 1 failures.

    • 0.adc_ctrl_csr_bit_bash.25265891423566380555942477067049283829049137697408385029225002649149222213233
      Line 163, in log /nightly/current_run/scratch/master/adc_ctrl-sim-xcelium/0.adc_ctrl_csr_bit_bash/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/adc_ctrl-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_fsm.sv,382): (time 2604770919 PS) Assertion tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.LpSampleCntCfg_M has failed
        UVM_ERROR @ 2604770919 ps: (adc_ctrl_fsm.sv:382) [ASSERT FAILED] LpSampleCntCfg_M
        UVM_INFO @ 2604770919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---