EDN Simulation Results

Monday September 15 2025 00:04:07 UTC

GitHub Revision: c127aed

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	3.000s	20.002us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	3.000s	22.700us	1	1	100.00
V1	csr_rw	edn_csr_rw	3.000s	21.486us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	4.000s	92.354us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	3.000s	300.040us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	3.000s	79.541us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	3.000s	21.486us	1	1	100.00
		edn_csr_aliasing	3.000s	300.040us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	4.000s	86.074us	1	1	100.00
V2	csrng_commands	edn_genbits	4.000s	86.074us	1	1	100.00
V2	genbits	edn_genbits	4.000s	86.074us	1	1	100.00
V2	interrupts	edn_intr	3.000s	24.424us	1	1	100.00
V2	alerts	edn_alert	4.000s	102.827us	1	1	100.00
V2	errs	edn_err	3.000s	47.584us	0	1	0.00
V2	disable	edn_disable	3.000s	22.374us	1	1	100.00
		edn_disable_auto_req_mode	3.000s	50.351us	1	1	100.00
V2	stress_all	edn_stress_all	10.000s	526.981us	1	1	100.00
V2	intr_test	edn_intr_test	3.000s	36.602us	1	1	100.00
V2	alert_test	edn_alert_test	3.000s	181.294us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	5.000s	217.594us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	5.000s	217.594us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	3.000s	22.700us	1	1	100.00
		edn_csr_rw	3.000s	21.486us	1	1	100.00
		edn_csr_aliasing	3.000s	300.040us	1	1	100.00
		edn_same_csr_outstanding	4.000s	39.204us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	3.000s	22.700us	1	1	100.00
		edn_csr_rw	3.000s	21.486us	1	1	100.00
		edn_csr_aliasing	3.000s	300.040us	1	1	100.00
		edn_same_csr_outstanding	4.000s	39.204us	1	1	100.00
V2		TOTAL			10	11	90.91
V2S	tl_intg_err	edn_sec_cm	10.000s	1.855ms	1	1	100.00
		edn_tl_intg_err	4.000s	99.523us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	3.000s	19.976us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	4.000s	102.827us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	10.000s	1.855ms	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	10.000s	1.855ms	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	10.000s	1.855ms	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	10.000s	1.855ms	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	4.000s	102.827us	1	1	100.00
		edn_sec_cm	10.000s	1.855ms	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	4.000s	102.827us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	4.000s	99.523us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	52.000s	2.027ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			20	21	95.24

Failure Buckets

• xmsim: *E,ASRTST (/nightly/current_run/scratch/master/edn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_edn_*/rtl/edn_main_sm.sv,42): Assertion u_state_regs_A has failed has 1 failures:
  • Test edn_err has 1 failures.

    • 0.edn_err.8568763989441013851680858723471269814635968945551241263978927361212910677124
      Line 142, in log /nightly/current_run/scratch/master/edn-sim-xcelium/0.edn_err/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/edn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv,42): (time 47584440 PS) Assertion tb.dut.u_edn_core.u_edn_main_sm.u_state_regs_A has failed
        UVM_ERROR @  47584440 ps: (edn_main_sm.sv:42) [ASSERT FAILED] u_state_regs_A
        UVM_INFO @  47584440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---