HMAC Simulation Results

Monday September 15 2025 00:04:07 UTC

GitHub Revision: c127aed

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 21.000s 3.610ms 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 4.000s 83.548us 1 1 100.00
V1 csr_rw hmac_csr_rw 3.000s 18.915us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 12.000s 2.051ms 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 12.000s 1.751ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 2.000m 9.144ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 3.000s 18.915us 1 1 100.00
hmac_csr_aliasing 12.000s 1.751ms 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 48.000s 12.632ms 1 1 100.00
V2 back_pressure hmac_back_pressure 1.183m 3.173ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 18.000s 337.668us 1 1 100.00
hmac_test_sha384_vectors 43.000s 972.105us 1 1 100.00
hmac_test_sha512_vectors 11.467m 44.508ms 1 1 100.00
hmac_test_hmac256_vectors 16.000s 500.911us 1 1 100.00
hmac_test_hmac384_vectors 17.000s 255.147us 1 1 100.00
hmac_test_hmac512_vectors 22.000s 694.862us 1 1 100.00
V2 burst_wr hmac_burst_wr 48.000s 1.891ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 5.833m 4.540ms 1 1 100.00
V2 error hmac_error 43.000s 9.434ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 58.000s 5.484ms 1 1 100.00
V2 save_and_restore hmac_smoke 21.000s 3.610ms 1 1 100.00
hmac_long_msg 48.000s 12.632ms 1 1 100.00
hmac_back_pressure 1.183m 3.173ms 1 1 100.00
hmac_datapath_stress 5.833m 4.540ms 1 1 100.00
hmac_burst_wr 48.000s 1.891ms 1 1 100.00
hmac_stress_all 59.000s 29.558ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 21.000s 3.610ms 1 1 100.00
hmac_long_msg 48.000s 12.632ms 1 1 100.00
hmac_back_pressure 1.183m 3.173ms 1 1 100.00
hmac_datapath_stress 5.833m 4.540ms 1 1 100.00
hmac_wipe_secret 58.000s 5.484ms 1 1 100.00
hmac_test_sha256_vectors 18.000s 337.668us 1 1 100.00
hmac_test_sha384_vectors 43.000s 972.105us 1 1 100.00
hmac_test_sha512_vectors 11.467m 44.508ms 1 1 100.00
hmac_test_hmac256_vectors 16.000s 500.911us 1 1 100.00
hmac_test_hmac384_vectors 17.000s 255.147us 1 1 100.00
hmac_test_hmac512_vectors 22.000s 694.862us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 21.000s 3.610ms 1 1 100.00
hmac_long_msg 48.000s 12.632ms 1 1 100.00
hmac_back_pressure 1.183m 3.173ms 1 1 100.00
hmac_datapath_stress 5.833m 4.540ms 1 1 100.00
hmac_burst_wr 48.000s 1.891ms 1 1 100.00
hmac_error 43.000s 9.434ms 1 1 100.00
hmac_wipe_secret 58.000s 5.484ms 1 1 100.00
hmac_test_sha256_vectors 18.000s 337.668us 1 1 100.00
hmac_test_sha384_vectors 43.000s 972.105us 1 1 100.00
hmac_test_sha512_vectors 11.467m 44.508ms 1 1 100.00
hmac_test_hmac256_vectors 16.000s 500.911us 1 1 100.00
hmac_test_hmac384_vectors 17.000s 255.147us 1 1 100.00
hmac_test_hmac512_vectors 22.000s 694.862us 1 1 100.00
hmac_stress_all 59.000s 29.558ms 1 1 100.00
V2 stress_all hmac_stress_all 59.000s 29.558ms 1 1 100.00
V2 alert_test hmac_alert_test 3.000s 13.145us 1 1 100.00
V2 intr_test hmac_intr_test 3.000s 44.578us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 5.000s 127.260us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 5.000s 127.260us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 4.000s 83.548us 1 1 100.00
hmac_csr_rw 3.000s 18.915us 1 1 100.00
hmac_csr_aliasing 12.000s 1.751ms 1 1 100.00
hmac_same_csr_outstanding 4.000s 244.484us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 4.000s 83.548us 1 1 100.00
hmac_csr_rw 3.000s 18.915us 1 1 100.00
hmac_csr_aliasing 12.000s 1.751ms 1 1 100.00
hmac_same_csr_outstanding 4.000s 244.484us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 4.000s 166.667us 1 1 100.00
hmac_tl_intg_err 6.000s 115.452us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 6.000s 115.452us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 21.000s 3.610ms 1 1 100.00
V3 stress_reset hmac_stress_reset 6.000s 525.109us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 45.000s 4.796ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 10.000s 572.243us 1 1 100.00
TOTAL 28 28 100.00