c127aed| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 0 | 1 | 0.00 | ||
| V1 | target_smoke | i2c_target_smoke | 30.000s | 4.613ms | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 3.000s | 38.862us | 1 | 1 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 3.000s | 44.098us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 6.000s | 218.357us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 4.000s | 126.453us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 3.000s | 68.358us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 3.000s | 44.098us | 1 | 1 | 100.00 |
| i2c_csr_aliasing | 4.000s | 126.453us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 6 | 7 | 85.71 | |||
| V2 | host_error_intr | i2c_host_error_intr | 4.000s | 341.053us | 1 | 1 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 0 | 1 | 0.00 | ||
| V2 | host_maxperf | i2c_host_perf | 13.000s | 503.186us | 1 | 1 | 100.00 |
| V2 | host_override | i2c_host_override | 3.000s | 186.164us | 1 | 1 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 0 | 1 | 0.00 | ||
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 0 | 1 | 0.00 | ||
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 4.000s | 92.797us | 1 | 1 | 100.00 |
| i2c_host_fifo_fmt_empty | 44.983m | 410.389us | 1 | 1 | 100.00 | ||
| i2c_host_fifo_reset_rx | 0 | 1 | 0.00 | ||||
| V2 | host_fifo_full | i2c_host_fifo_full | 0 | 1 | 0.00 | ||
| V2 | host_timeout | i2c_host_stretch_timeout | 7.450m | 1.797ms | 1 | 1 | 100.00 |
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 15.000s | 424.521us | 1 | 1 | 100.00 |
| V2 | target_glitch | i2c_target_glitch | 6.000s | 1.692ms | 0 | 1 | 0.00 |
| V2 | target_stress_all | i2c_target_stress_all | 0 | 1 | 0.00 | ||
| V2 | target_maxperf | i2c_target_perf | 55.117m | 1.325ms | 1 | 1 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 0 | 1 | 0.00 | ||
| i2c_target_intr_smoke | 0 | 1 | 0.00 | ||||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 5.000s | 221.240us | 1 | 1 | 100.00 |
| i2c_target_fifo_reset_tx | 6.217m | 368.995us | 1 | 1 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 47.000s | 8.444ms | 1 | 1 | 100.00 |
| i2c_target_stress_rd | 0 | 1 | 0.00 | ||||
| i2c_target_intr_stress_wr | 0 | 1 | 0.00 | ||||
| V2 | target_timeout | i2c_target_timeout | 4.783m | 1.316ms | 1 | 1 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 0 | 1 | 0.00 | ||
| V2 | bad_address | i2c_target_bad_addr | 11.000s | 926.621us | 1 | 1 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 7.000s | 280.519us | 1 | 1 | 100.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 5.000s | 1.204ms | 1 | 1 | 100.00 |
| i2c_target_fifo_watermarks_tx | 5.000s | 139.975us | 1 | 1 | 100.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 13.000s | 503.186us | 1 | 1 | 100.00 |
| i2c_host_perf_precise | 21.000s | 421.258us | 1 | 1 | 100.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 7.450m | 1.797ms | 1 | 1 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 6.000s | 182.104us | 1 | 1 | 100.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 12.000s | 4.971ms | 1 | 1 | 100.00 |
| i2c_target_nack_acqfull_addr | 32.000s | 465.948us | 1 | 1 | 100.00 | ||
| i2c_target_nack_txstretch | 50.233m | 256.885us | 1 | 1 | 100.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 10.000s | 306.034us | 1 | 1 | 100.00 |
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 7.000s | 839.846us | 1 | 1 | 100.00 |
| V2 | alert_test | i2c_alert_test | 3.000s | 17.937us | 1 | 1 | 100.00 |
| V2 | intr_test | i2c_intr_test | 3.000s | 17.147us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 4.000s | 56.918us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 4.000s | 56.918us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 3.000s | 38.862us | 1 | 1 | 100.00 |
| i2c_csr_rw | 3.000s | 44.098us | 1 | 1 | 100.00 | ||
| i2c_csr_aliasing | 4.000s | 126.453us | 1 | 1 | 100.00 | ||
| i2c_same_csr_outstanding | 3.000s | 28.910us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 3.000s | 38.862us | 1 | 1 | 100.00 |
| i2c_csr_rw | 3.000s | 44.098us | 1 | 1 | 100.00 | ||
| i2c_csr_aliasing | 4.000s | 126.453us | 1 | 1 | 100.00 | ||
| i2c_same_csr_outstanding | 3.000s | 28.910us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 27 | 38 | 71.05 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 4.000s | 66.806us | 1 | 1 | 100.00 |
| i2c_sec_cm | 3.000s | 82.150us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 4.000s | 66.806us | 1 | 1 | 100.00 |
| V2S | TOTAL | 2 | 2 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 0 | 1 | 0.00 | ||
| V3 | target_error_intr | i2c_target_unexp_stop | 3.000s | 91.159us | 0 | 1 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 18.000s | 644.015us | 0 | 1 | 0.00 |
| V3 | TOTAL | 0 | 3 | 0.00 | |||
| TOTAL | 35 | 50 | 70.00 |
Job timed out after * minutes has 12 failures:
Test i2c_host_smoke has 1 failures.
0.i2c_host_smoke.81911581439667113796304862849437291164420713767431129206937827433933227099313
Log /nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_host_smoke/latest/run.log
Job timed out after 60 minutes
Test i2c_host_fifo_watermark has 1 failures.
0.i2c_host_fifo_watermark.29633950822937789281947690952716488031469579733397386738039183526089201081393
Log /nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_host_fifo_watermark/latest/run.log
Job timed out after 60 minutes
Test i2c_host_fifo_overflow has 1 failures.
0.i2c_host_fifo_overflow.44670069392979454387678063976943847973608235996186242716249694508618617035860
Log /nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_host_fifo_overflow/latest/run.log
Job timed out after 60 minutes
Test i2c_host_fifo_reset_rx has 1 failures.
0.i2c_host_fifo_reset_rx.25680191984528079104561759498613356912895264512747803370309929736649835641130
Log /nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_host_fifo_reset_rx/latest/run.log
Job timed out after 60 minutes
Test i2c_host_fifo_full has 1 failures.
0.i2c_host_fifo_full.113466544638019017233414048517190313570140457180769355906246197701090279234609
Log /nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_host_fifo_full/latest/run.log
Job timed out after 60 minutes
... and 7 more tests.
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:
0.i2c_target_glitch.22356988437171721751219070855939141341645201882300922456912958078934538913159
Line 90, in log /nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_target_glitch/latest/run.log
UVM_ERROR @ 1691596182 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
UVM_INFO @ 1691596182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:
0.i2c_target_unexp_stop.114657149733295199709564693948470683477420855015838060262247238287310970528428
Line 84, in log /nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 91158756 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 68 [0x44])
UVM_INFO @ 91158756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:946) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
0.i2c_target_stress_all_with_rand_reset.18942627491851647254204034718394248969089373237091645638088552313433409406561
Line 92, in log /nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 644015175 ps: (cip_base_vseq.sv:946) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 644015175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---