KEYMGR Simulation Results

Monday September 15 2025 00:04:07 UTC

GitHub Revision: c127aed

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke keymgr_smoke 12.000s 628.633us 1 1 100.00
V1 random keymgr_random 45.724s 0 1 0.00
V1 csr_hw_reset keymgr_csr_hw_reset 9.000s 88.556us 1 1 100.00
V1 csr_rw keymgr_csr_rw 10.000s 51.103us 1 1 100.00
V1 csr_bit_bash keymgr_csr_bit_bash 19.000s 1.791ms 1 1 100.00
V1 csr_aliasing keymgr_csr_aliasing 14.000s 126.741us 1 1 100.00
V1 csr_mem_rw_with_rand_reset keymgr_csr_mem_rw_with_rand_reset 9.000s 30.717us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr keymgr_csr_rw 10.000s 51.103us 1 1 100.00
keymgr_csr_aliasing 14.000s 126.741us 1 1 100.00
V1 TOTAL 6 7 85.71
V2 cfgen_during_op keymgr_cfg_regwen 45.543s 0 1 0.00
V2 sideload keymgr_sideload 11.000s 41.543us 1 1 100.00
keymgr_sideload_kmac 12.000s 394.508us 1 1 100.00
keymgr_sideload_aes 13.000s 202.709us 1 1 100.00
keymgr_sideload_otbn 17.000s 628.009us 1 1 100.00
V2 direct_to_disabled_state keymgr_direct_to_disabled 45.434s 0 1 0.00
V2 lc_disable keymgr_lc_disable 44.329s 0 1 0.00
V2 kmac_error_response keymgr_kmac_rsp_err 45.641s 0 1 0.00
V2 invalid_sw_input keymgr_sw_invalid_input 44.327s 0 1 0.00
V2 invalid_hw_input keymgr_hwsw_invalid_input 45.640s 0 1 0.00
V2 sync_async_fault_cross keymgr_sync_async_fault_cross 19.000s 1.530ms 1 1 100.00
V2 stress_all keymgr_stress_all 45.577s 0 1 0.00
V2 intr_test keymgr_intr_test 10.000s 51.367us 1 1 100.00
V2 alert_test keymgr_alert_test 10.000s 10.795us 1 1 100.00
V2 tl_d_oob_addr_access keymgr_tl_errors 10.000s 99.059us 1 1 100.00
V2 tl_d_illegal_access keymgr_tl_errors 10.000s 99.059us 1 1 100.00
V2 tl_d_outstanding_access keymgr_csr_hw_reset 9.000s 88.556us 1 1 100.00
keymgr_csr_rw 10.000s 51.103us 1 1 100.00
keymgr_csr_aliasing 14.000s 126.741us 1 1 100.00
keymgr_same_csr_outstanding 10.000s 25.654us 1 1 100.00
V2 tl_d_partial_access keymgr_csr_hw_reset 9.000s 88.556us 1 1 100.00
keymgr_csr_rw 10.000s 51.103us 1 1 100.00
keymgr_csr_aliasing 14.000s 126.741us 1 1 100.00
keymgr_same_csr_outstanding 10.000s 25.654us 1 1 100.00
V2 TOTAL 9 16 56.25
V2S sec_cm_additional_check keymgr_sec_cm 15.000s 1.285ms 1 1 100.00
V2S tl_intg_err keymgr_sec_cm 15.000s 1.285ms 1 1 100.00
keymgr_tl_intg_err 11.000s 127.709us 1 1 100.00
V2S shadow_reg_update_error keymgr_shadow_reg_errors 10.000s 241.699us 1 1 100.00
V2S shadow_reg_read_clear_staged_value keymgr_shadow_reg_errors 10.000s 241.699us 1 1 100.00
V2S shadow_reg_storage_error keymgr_shadow_reg_errors 10.000s 241.699us 1 1 100.00
V2S shadowed_reset_glitch keymgr_shadow_reg_errors 10.000s 241.699us 1 1 100.00
V2S shadow_reg_update_error_with_csr_rw keymgr_shadow_reg_errors_with_csr_rw 16.000s 548.181us 1 1 100.00
V2S prim_count_check keymgr_sec_cm 15.000s 1.285ms 1 1 100.00
V2S prim_fsm_check keymgr_sec_cm 15.000s 1.285ms 1 1 100.00
V2S sec_cm_bus_integrity keymgr_tl_intg_err 11.000s 127.709us 1 1 100.00
V2S sec_cm_config_shadow keymgr_shadow_reg_errors 10.000s 241.699us 1 1 100.00
V2S sec_cm_op_config_regwen keymgr_cfg_regwen 45.543s 0 1 0.00
V2S sec_cm_reseed_config_regwen keymgr_random 45.724s 0 1 0.00
keymgr_csr_rw 10.000s 51.103us 1 1 100.00
V2S sec_cm_sw_binding_config_regwen keymgr_random 45.724s 0 1 0.00
keymgr_csr_rw 10.000s 51.103us 1 1 100.00
V2S sec_cm_max_key_ver_config_regwen keymgr_random 45.724s 0 1 0.00
keymgr_csr_rw 10.000s 51.103us 1 1 100.00
V2S sec_cm_lc_ctrl_intersig_mubi keymgr_lc_disable 44.329s 0 1 0.00
V2S sec_cm_constants_consistency keymgr_hwsw_invalid_input 45.640s 0 1 0.00
V2S sec_cm_intersig_consistency keymgr_hwsw_invalid_input 45.640s 0 1 0.00
V2S sec_cm_hw_key_sw_noaccess keymgr_random 45.724s 0 1 0.00
V2S sec_cm_output_keys_ctrl_redun keymgr_sideload_protect 10.000s 23.130us 1 1 100.00
V2S sec_cm_ctrl_fsm_sparse keymgr_sec_cm 15.000s 1.285ms 1 1 100.00
V2S sec_cm_data_fsm_sparse keymgr_sec_cm 15.000s 1.285ms 1 1 100.00
V2S sec_cm_ctrl_fsm_local_esc keymgr_sec_cm 15.000s 1.285ms 1 1 100.00
V2S sec_cm_ctrl_fsm_consistency keymgr_custom_cm 45.642s 0 1 0.00
V2S sec_cm_ctrl_fsm_global_esc keymgr_lc_disable 44.329s 0 1 0.00
V2S sec_cm_ctrl_ctr_redun keymgr_sec_cm 15.000s 1.285ms 1 1 100.00
V2S sec_cm_kmac_if_fsm_sparse keymgr_sec_cm 15.000s 1.285ms 1 1 100.00
V2S sec_cm_kmac_if_ctr_redun keymgr_sec_cm 15.000s 1.285ms 1 1 100.00
V2S sec_cm_kmac_if_cmd_ctrl_consistency keymgr_custom_cm 45.642s 0 1 0.00
V2S sec_cm_kmac_if_done_ctrl_consistency keymgr_custom_cm 45.642s 0 1 0.00
V2S sec_cm_reseed_ctr_redun keymgr_sec_cm 15.000s 1.285ms 1 1 100.00
V2S sec_cm_side_load_sel_ctrl_consistency keymgr_custom_cm 45.642s 0 1 0.00
V2S sec_cm_sideload_ctrl_fsm_sparse keymgr_sec_cm 15.000s 1.285ms 1 1 100.00
V2S sec_cm_ctrl_key_integrity keymgr_custom_cm 45.642s 0 1 0.00
V2S TOTAL 5 6 83.33
V3 stress_all_with_rand_reset keymgr_stress_all_with_rand_reset 45.805s 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 20 30 66.67

Failure Buckets