KMAC/MASKED Simulation Results

Monday September 15 2025 00:04:07 UTC

GitHub Revision: c127aed

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke kmac_smoke 1.950m 15.931ms 0 1 0.00
V1 csr_hw_reset kmac_csr_hw_reset 3.000s 36.812us 0 1 0.00
V1 csr_rw kmac_csr_rw 3.000s 45.350us 0 1 0.00
V1 csr_bit_bash kmac_csr_bit_bash 31.000s 1.280ms 0 1 0.00
V1 csr_aliasing kmac_csr_aliasing 16.000s 9.610ms 0 1 0.00
V1 csr_mem_rw_with_rand_reset kmac_csr_mem_rw_with_rand_reset 5.000s 63.345us 0 1 0.00
V1 regwen_csr_and_corresponding_lockable_csr kmac_csr_rw 3.000s 45.350us 0 1 0.00
kmac_csr_aliasing 16.000s 9.610ms 0 1 0.00
V1 mem_walk kmac_mem_walk 3.000s 35.588us 0 1 0.00
V1 mem_partial_access kmac_mem_partial_access 4.000s 61.320us 0 1 0.00
V1 TOTAL 0 8 0.00
V2 long_msg_and_output kmac_long_msg_and_output 33.017m 218.474ms 0 1 0.00
V2 burst_write kmac_burst_write 3.267m 5.753ms 0 1 0.00
V2 test_vectors kmac_test_vectors_sha3_224 53.000s 5.610ms 0 1 0.00
kmac_test_vectors_sha3_256 56.000s 3.799ms 0 1 0.00
kmac_test_vectors_sha3_384 37.783m 137.230ms 0 1 0.00
kmac_test_vectors_sha3_512 29.000s 1.035ms 0 1 0.00
kmac_test_vectors_shake_128 5.933m 54.523ms 0 1 0.00
kmac_test_vectors_shake_256 8.567m 14.118ms 0 1 0.00
kmac_test_vectors_kmac 7.000s 319.341us 0 1 0.00
kmac_test_vectors_kmac_xof 6.000s 168.376us 0 1 0.00
V2 sideload kmac_sideload 1.217m 3.120ms 0 1 0.00
V2 app kmac_app 3.200m 6.254ms 0 1 0.00
V2 app_with_partial_data kmac_app_with_partial_data 4.933m 30.989ms 0 1 0.00
V2 entropy_refresh kmac_entropy_refresh 7.767m 61.670ms 0 1 0.00
V2 error kmac_error 1.467m 2.424ms 0 1 0.00
V2 key_error kmac_key_error 21.000s 2.580ms 0 1 0.00
V2 sideload_invalid kmac_sideload_invalid 11.000s 223.112us 0 1 0.00
V2 edn_timeout_error kmac_edn_timeout_error 4.000s 0 1 0.00
V2 entropy_mode_error kmac_entropy_mode_error 4.000s 0 1 0.00
V2 entropy_ready_error kmac_entropy_ready_error 1.017m 29.048ms 0 1 0.00
V2 lc_escalation kmac_lc_escalation 10.000s 514.599us 0 1 0.00
V2 stress_all kmac_stress_all 30.583m 47.333ms 0 1 0.00
V2 intr_test kmac_intr_test 3.000s 30.879us 0 1 0.00
V2 alert_test kmac_alert_test 4.000s 20.939us 0 1 0.00
V2 tl_d_oob_addr_access kmac_tl_errors 6.000s 379.680us 0 1 0.00
V2 tl_d_illegal_access kmac_tl_errors 6.000s 379.680us 0 1 0.00
V2 tl_d_outstanding_access kmac_csr_hw_reset 3.000s 36.812us 0 1 0.00
kmac_csr_rw 3.000s 45.350us 0 1 0.00
kmac_csr_aliasing 16.000s 9.610ms 0 1 0.00
kmac_same_csr_outstanding 6.000s 134.894us 0 1 0.00
V2 tl_d_partial_access kmac_csr_hw_reset 3.000s 36.812us 0 1 0.00
kmac_csr_rw 3.000s 45.350us 0 1 0.00
kmac_csr_aliasing 16.000s 9.610ms 0 1 0.00
kmac_same_csr_outstanding 6.000s 134.894us 0 1 0.00
V2 TOTAL 0 26 0.00
V2S shadow_reg_update_error kmac_shadow_reg_errors 4.000s 155.749us 0 1 0.00
V2S shadow_reg_read_clear_staged_value kmac_shadow_reg_errors 4.000s 155.749us 0 1 0.00
V2S shadow_reg_storage_error kmac_shadow_reg_errors 4.000s 155.749us 0 1 0.00
V2S shadowed_reset_glitch kmac_shadow_reg_errors 4.000s 155.749us 0 1 0.00
V2S shadow_reg_update_error_with_csr_rw kmac_shadow_reg_errors_with_csr_rw 9.000s 618.824us 0 1 0.00
V2S tl_intg_err kmac_sec_cm 1.617m 11.166ms 0 1 0.00
kmac_tl_intg_err 9.000s 262.341us 0 1 0.00
V2S sec_cm_bus_integrity kmac_tl_intg_err 9.000s 262.341us 0 1 0.00
V2S sec_cm_lc_escalate_en_intersig_mubi kmac_lc_escalation 10.000s 514.599us 0 1 0.00
V2S sec_cm_sw_key_key_masking kmac_smoke 1.950m 15.931ms 0 1 0.00
V2S sec_cm_key_sideload kmac_sideload 1.217m 3.120ms 0 1 0.00
V2S sec_cm_cfg_shadowed_config_shadow kmac_shadow_reg_errors 4.000s 155.749us 0 1 0.00
V2S sec_cm_fsm_sparse kmac_sec_cm 1.617m 11.166ms 0 1 0.00
V2S sec_cm_ctr_redun kmac_sec_cm 1.617m 11.166ms 0 1 0.00
V2S sec_cm_packer_ctr_redun kmac_sec_cm 1.617m 11.166ms 0 1 0.00
V2S sec_cm_cfg_shadowed_config_regwen kmac_smoke 1.950m 15.931ms 0 1 0.00
V2S sec_cm_fsm_global_esc kmac_lc_escalation 10.000s 514.599us 0 1 0.00
V2S sec_cm_fsm_local_esc kmac_sec_cm 1.617m 11.166ms 0 1 0.00
V2S sec_cm_absorbed_ctrl_mubi kmac_mubi 6.183m 35.401ms 0 1 0.00
V2S sec_cm_sw_cmd_ctrl_sparse kmac_smoke 1.950m 15.931ms 0 1 0.00
V2S TOTAL 0 5 0.00
V3 stress_all_with_rand_reset kmac_stress_all_with_rand_reset 3.283m 15.866ms 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 0 40 0.00

Failure Buckets