KMAC/UNMASKED Simulation Results

Monday September 15 2025 00:04:07 UTC

GitHub Revision: c127aed

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke kmac_smoke 23.000s 946.366us 0 1 0.00
V1 csr_hw_reset kmac_csr_hw_reset 4.000s 94.254us 0 1 0.00
V1 csr_rw kmac_csr_rw 4.000s 32.549us 0 1 0.00
V1 csr_bit_bash kmac_csr_bit_bash 19.000s 2.319ms 0 1 0.00
V1 csr_aliasing kmac_csr_aliasing 7.000s 76.349us 0 1 0.00
V1 csr_mem_rw_with_rand_reset kmac_csr_mem_rw_with_rand_reset 4.000s 312.847us 0 1 0.00
V1 regwen_csr_and_corresponding_lockable_csr kmac_csr_rw 4.000s 32.549us 0 1 0.00
kmac_csr_aliasing 7.000s 76.349us 0 1 0.00
V1 mem_walk kmac_mem_walk 3.000s 15.522us 0 1 0.00
V1 mem_partial_access kmac_mem_partial_access 4.000s 34.856us 0 1 0.00
V1 TOTAL 0 8 0.00
V2 long_msg_and_output kmac_long_msg_and_output 1.354h 253.835ms 0 1 0.00
V2 burst_write kmac_burst_write 9.183m 21.004ms 0 1 0.00
V2 test_vectors kmac_test_vectors_sha3_224 1.483m 41.834ms 0 1 0.00
kmac_test_vectors_sha3_256 47.983m 165.883ms 0 1 0.00
kmac_test_vectors_sha3_384 25.733m 42.275ms 0 1 0.00
kmac_test_vectors_sha3_512 30.000s 1.471ms 0 1 0.00
kmac_test_vectors_shake_128 44.283m 152.993ms 0 1 0.00
kmac_test_vectors_shake_256 2.417m 17.146ms 0 1 0.00
kmac_test_vectors_kmac 5.000s 31.676us 0 1 0.00
kmac_test_vectors_kmac_xof 7.000s 427.854us 0 1 0.00
V2 sideload kmac_sideload 6.700m 13.623ms 0 1 0.00
V2 app kmac_app 2.067m 7.202ms 0 1 0.00
V2 app_with_partial_data kmac_app_with_partial_data 5.450m 9.371ms 0 1 0.00
V2 entropy_refresh kmac_entropy_refresh 3.717m 35.229ms 0 1 0.00
V2 error kmac_error 4.983m 16.645ms 0 1 0.00
V2 key_error kmac_key_error 17.000s 1.286ms 0 1 0.00
V2 sideload_invalid kmac_sideload_invalid 1.317m 10.266ms 0 1 0.00
V2 edn_timeout_error kmac_edn_timeout_error 4.000s 0 1 0.00
V2 entropy_mode_error kmac_entropy_mode_error 4.000s 0 1 0.00
V2 entropy_ready_error kmac_entropy_ready_error 25.000s 3.404ms 0 1 0.00
V2 lc_escalation kmac_lc_escalation 23.000s 1.654ms 0 1 0.00
V2 stress_all kmac_stress_all 17.600m 9.667ms 0 1 0.00
V2 intr_test kmac_intr_test 3.000s 25.205us 0 1 0.00
V2 alert_test kmac_alert_test 3.000s 16.428us 0 1 0.00
V2 tl_d_oob_addr_access kmac_tl_errors 6.000s 122.717us 0 1 0.00
V2 tl_d_illegal_access kmac_tl_errors 6.000s 122.717us 0 1 0.00
V2 tl_d_outstanding_access kmac_csr_hw_reset 4.000s 94.254us 0 1 0.00
kmac_csr_rw 4.000s 32.549us 0 1 0.00
kmac_csr_aliasing 7.000s 76.349us 0 1 0.00
kmac_same_csr_outstanding 5.000s 153.611us 0 1 0.00
V2 tl_d_partial_access kmac_csr_hw_reset 4.000s 94.254us 0 1 0.00
kmac_csr_rw 4.000s 32.549us 0 1 0.00
kmac_csr_aliasing 7.000s 76.349us 0 1 0.00
kmac_same_csr_outstanding 5.000s 153.611us 0 1 0.00
V2 TOTAL 0 26 0.00
V2S shadow_reg_update_error kmac_shadow_reg_errors 5.000s 148.075us 0 1 0.00
V2S shadow_reg_read_clear_staged_value kmac_shadow_reg_errors 5.000s 148.075us 0 1 0.00
V2S shadow_reg_storage_error kmac_shadow_reg_errors 5.000s 148.075us 0 1 0.00
V2S shadowed_reset_glitch kmac_shadow_reg_errors 5.000s 148.075us 0 1 0.00
V2S shadow_reg_update_error_with_csr_rw kmac_shadow_reg_errors_with_csr_rw 7.000s 529.112us 0 1 0.00
V2S tl_intg_err kmac_sec_cm 1.050m 8.656ms 0 1 0.00
kmac_tl_intg_err 7.000s 777.514us 0 1 0.00
V2S sec_cm_bus_integrity kmac_tl_intg_err 7.000s 777.514us 0 1 0.00
V2S sec_cm_lc_escalate_en_intersig_mubi kmac_lc_escalation 23.000s 1.654ms 0 1 0.00
V2S sec_cm_sw_key_key_masking kmac_smoke 23.000s 946.366us 0 1 0.00
V2S sec_cm_key_sideload kmac_sideload 6.700m 13.623ms 0 1 0.00
V2S sec_cm_cfg_shadowed_config_shadow kmac_shadow_reg_errors 5.000s 148.075us 0 1 0.00
V2S sec_cm_fsm_sparse kmac_sec_cm 1.050m 8.656ms 0 1 0.00
V2S sec_cm_ctr_redun kmac_sec_cm 1.050m 8.656ms 0 1 0.00
V2S sec_cm_packer_ctr_redun kmac_sec_cm 1.050m 8.656ms 0 1 0.00
V2S sec_cm_cfg_shadowed_config_regwen kmac_smoke 23.000s 946.366us 0 1 0.00
V2S sec_cm_fsm_global_esc kmac_lc_escalation 23.000s 1.654ms 0 1 0.00
V2S sec_cm_fsm_local_esc kmac_sec_cm 1.050m 8.656ms 0 1 0.00
V2S sec_cm_absorbed_ctrl_mubi kmac_mubi 4.317m 4.335ms 0 1 0.00
V2S sec_cm_sw_cmd_ctrl_sparse kmac_smoke 23.000s 946.366us 0 1 0.00
V2S TOTAL 0 5 0.00
V3 stress_all_with_rand_reset kmac_stress_all_with_rand_reset 1.550m 2.881ms 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 0 40 0.00

Failure Buckets