OTBN Simulation Results

Monday September 15 2025 00:04:07 UTC

GitHub Revision: c127aed

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke otbn_smoke 17.000s 83.062us 0 1 0.00
V1 single_binary otbn_single 13.000s 31.114us 0 1 0.00
V1 csr_hw_reset otbn_csr_hw_reset 9.000s 25.526us 1 1 100.00
V1 csr_rw otbn_csr_rw 5.000s 41.198us 1 1 100.00
V1 csr_bit_bash otbn_csr_bit_bash 10.000s 34.281us 1 1 100.00
V1 csr_aliasing otbn_csr_aliasing 7.000s 21.308us 1 1 100.00
V1 csr_mem_rw_with_rand_reset otbn_csr_mem_rw_with_rand_reset 9.000s 35.732us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr otbn_csr_rw 5.000s 41.198us 1 1 100.00
otbn_csr_aliasing 7.000s 21.308us 1 1 100.00
V1 mem_walk otbn_mem_walk 1.100m 1.878ms 1 1 100.00
V1 mem_partial_access otbn_mem_partial_access 15.000s 729.284us 1 1 100.00
V1 TOTAL 7 9 77.78
V2 reset_recovery otbn_reset 48.000s 300.257us 0 1 0.00
V2 multi_error otbn_multi_err 1.450m 164.989us 0 1 0.00
V2 back_to_back otbn_multi 24.000s 48.550us 0 1 0.00
V2 stress_all otbn_stress_all 1.017m 440.765us 0 1 0.00
V2 lc_escalation otbn_escalate 10.000s 226.956us 0 1 0.00
V2 zero_state_err_urnd otbn_zero_state_err_urnd 9.000s 24.577us 1 1 100.00
V2 sw_errs_fatal_chk otbn_sw_errs_fatal_chk 28.000s 74.593us 0 1 0.00
V2 alert_test otbn_alert_test 7.000s 55.469us 1 1 100.00
V2 intr_test otbn_intr_test 5.000s 124.582us 1 1 100.00
V2 tl_d_oob_addr_access otbn_tl_errors 8.000s 62.925us 1 1 100.00
V2 tl_d_illegal_access otbn_tl_errors 8.000s 62.925us 1 1 100.00
V2 tl_d_outstanding_access otbn_csr_hw_reset 9.000s 25.526us 1 1 100.00
otbn_csr_rw 5.000s 41.198us 1 1 100.00
otbn_csr_aliasing 7.000s 21.308us 1 1 100.00
otbn_same_csr_outstanding 7.000s 87.977us 1 1 100.00
V2 tl_d_partial_access otbn_csr_hw_reset 9.000s 25.526us 1 1 100.00
otbn_csr_rw 5.000s 41.198us 1 1 100.00
otbn_csr_aliasing 7.000s 21.308us 1 1 100.00
otbn_same_csr_outstanding 7.000s 87.977us 1 1 100.00
V2 TOTAL 5 11 45.45
V2S mem_integrity otbn_imem_err 12.000s 52.390us 0 1 0.00
otbn_dmem_err 11.000s 45.270us 0 1 0.00
V2S internal_integrity otbn_alu_bignum_mod_err 16.000s 98.938us 0 1 0.00
otbn_controller_ispr_rdata_err 12.000s 205.755us 0 1 0.00
otbn_mac_bignum_acc_err 15.000s 65.729us 0 1 0.00
otbn_urnd_err 8.000s 17.453us 0 1 0.00
V2S illegal_bus_access otbn_illegal_mem_acc 11.000s 43.057us 1 1 100.00
V2S otbn_mem_gnt_acc_err otbn_mem_gnt_acc_err 10.000s 34.673us 0 1 0.00
V2S otbn_non_sec_partial_wipe otbn_partial_wipe 7.000s 19.001us 0 1 0.00
V2S tl_intg_err otbn_sec_cm 4.850m 4.553ms 1 1 100.00
otbn_tl_intg_err 27.000s 137.342us 1 1 100.00
V2S passthru_mem_tl_intg_err otbn_passthru_mem_tl_intg_err 58.000s 241.801us 1 1 100.00
V2S prim_fsm_check otbn_sec_cm 4.850m 4.553ms 1 1 100.00
V2S prim_count_check otbn_sec_cm 4.850m 4.553ms 1 1 100.00
V2S sec_cm_mem_scramble otbn_smoke 17.000s 83.062us 0 1 0.00
V2S sec_cm_data_mem_integrity otbn_dmem_err 11.000s 45.270us 0 1 0.00
V2S sec_cm_instruction_mem_integrity otbn_imem_err 12.000s 52.390us 0 1 0.00
V2S sec_cm_bus_integrity otbn_tl_intg_err 27.000s 137.342us 1 1 100.00
V2S sec_cm_controller_fsm_global_esc otbn_escalate 10.000s 226.956us 0 1 0.00
V2S sec_cm_controller_fsm_local_esc otbn_imem_err 12.000s 52.390us 0 1 0.00
otbn_dmem_err 11.000s 45.270us 0 1 0.00
otbn_zero_state_err_urnd 9.000s 24.577us 1 1 100.00
otbn_illegal_mem_acc 11.000s 43.057us 1 1 100.00
otbn_sec_cm 4.850m 4.553ms 1 1 100.00
V2S sec_cm_controller_fsm_sparse otbn_sec_cm 4.850m 4.553ms 1 1 100.00
V2S sec_cm_scramble_key_sideload otbn_single 13.000s 31.114us 0 1 0.00
V2S sec_cm_scramble_ctrl_fsm_local_esc otbn_imem_err 12.000s 52.390us 0 1 0.00
otbn_dmem_err 11.000s 45.270us 0 1 0.00
otbn_zero_state_err_urnd 9.000s 24.577us 1 1 100.00
otbn_illegal_mem_acc 11.000s 43.057us 1 1 100.00
otbn_sec_cm 4.850m 4.553ms 1 1 100.00
V2S sec_cm_scramble_ctrl_fsm_sparse otbn_sec_cm 4.850m 4.553ms 1 1 100.00
V2S sec_cm_start_stop_ctrl_fsm_global_esc otbn_escalate 10.000s 226.956us 0 1 0.00
V2S sec_cm_start_stop_ctrl_fsm_local_esc otbn_imem_err 12.000s 52.390us 0 1 0.00
otbn_dmem_err 11.000s 45.270us 0 1 0.00
otbn_zero_state_err_urnd 9.000s 24.577us 1 1 100.00
otbn_illegal_mem_acc 11.000s 43.057us 1 1 100.00
otbn_sec_cm 4.850m 4.553ms 1 1 100.00
V2S sec_cm_start_stop_ctrl_fsm_sparse otbn_sec_cm 4.850m 4.553ms 1 1 100.00
V2S sec_cm_data_reg_sw_sca otbn_single 13.000s 31.114us 0 1 0.00
V2S sec_cm_ctrl_redun otbn_ctrl_redun 17.000s 68.431us 0 1 0.00
V2S sec_cm_pc_ctrl_flow_redun otbn_pc_ctrl_flow_redun 8.000s 36.124us 1 1 100.00
V2S sec_cm_rnd_bus_consistency otbn_rnd_sec_cm 1.017m 632.550us 0 1 0.00
V2S sec_cm_rnd_rng_digest otbn_rnd_sec_cm 1.017m 632.550us 0 1 0.00
V2S sec_cm_rf_base_data_reg_sw_integrity otbn_rf_base_intg_err 16.000s 31.310us 0 1 0.00
V2S sec_cm_rf_base_data_reg_sw_glitch_detect otbn_sec_cm 4.850m 4.553ms 1 1 100.00
V2S sec_cm_stack_wr_ptr_ctr_redun otbn_sec_cm 4.850m 4.553ms 1 1 100.00
V2S sec_cm_rf_bignum_data_reg_sw_integrity otbn_rf_bignum_intg_err 13.000s 217.155us 0 1 0.00
V2S sec_cm_rf_bignum_data_reg_sw_glitch_detect otbn_sec_cm 4.850m 4.553ms 1 1 100.00
V2S sec_cm_loop_stack_ctr_redun otbn_sec_cm 4.850m 4.553ms 1 1 100.00
V2S sec_cm_loop_stack_addr_integrity otbn_stack_addr_integ_chk 24.000s 38.685us 0 1 0.00
V2S sec_cm_call_stack_addr_integrity otbn_stack_addr_integ_chk 24.000s 38.685us 0 1 0.00
V2S sec_cm_start_stop_ctrl_state_consistency otbn_sec_wipe_err 10.000s 14.305us 0 1 0.00
V2S sec_cm_data_mem_sec_wipe otbn_single 13.000s 31.114us 0 1 0.00
V2S sec_cm_instruction_mem_sec_wipe otbn_single 13.000s 31.114us 0 1 0.00
V2S sec_cm_data_reg_sw_sec_wipe otbn_single 13.000s 31.114us 0 1 0.00
V2S sec_cm_write_mem_integrity otbn_multi 24.000s 48.550us 0 1 0.00
V2S sec_cm_ctrl_flow_count otbn_single 13.000s 31.114us 0 1 0.00
V2S sec_cm_ctrl_flow_sca otbn_single 13.000s 31.114us 0 1 0.00
V2S sec_cm_data_mem_sw_noaccess otbn_sw_no_acc 12.000s 106.435us 0 1 0.00
V2S sec_cm_key_sideload otbn_single 13.000s 31.114us 0 1 0.00
V2S sec_cm_tlul_fifo_ctr_redun otbn_sec_cm 4.850m 4.553ms 1 1 100.00
V2S TOTAL 5 20 25.00
V3 stress_all_with_rand_reset otbn_stress_all_with_rand_reset 5.950m 11.217ms 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 17 41 41.46

Failure Buckets