PATTGEN Simulation Results

Monday September 15 2025 00:04:07 UTC

GitHub Revision: `c127aed`

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	2.000s	62.101us	1	1	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	2.000s	15.103us	1	1	100.00
V1	csr_rw	pattgen_csr_rw	3.000s	52.062us	1	1	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	4.000s	63.406us	1	1	100.00
V1	csr_aliasing	pattgen_csr_aliasing	2.000s	40.452us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	3.000s	78.411us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	3.000s	52.062us	1	1	100.00
		pattgen_csr_aliasing	2.000s	40.452us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	perf	pattgen_perf	36.000s	52.652ms	1	1	100.00
V2	cnt_rollover	cnt_rollover	18.000s	398.326us	1	1	100.00
V2	error	pattgen_error	3.000s	83.551us	1	1	100.00
V2	stress_all	pattgen_stress_all	3.000s	114.702us	0	1	0.00
V2	alert_test	pattgen_alert_test	3.000s	13.473us	1	1	100.00
V2	intr_test	pattgen_intr_test	2.000s	104.114us	1	1	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	4.000s	83.964us	1	1	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	4.000s	83.964us	1	1	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	2.000s	15.103us	1	1	100.00
		pattgen_csr_rw	3.000s	52.062us	1	1	100.00
		pattgen_csr_aliasing	2.000s	40.452us	1	1	100.00
		pattgen_same_csr_outstanding	3.000s	12.613us	1	1	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	2.000s	15.103us	1	1	100.00
		pattgen_csr_rw	3.000s	52.062us	1	1	100.00
		pattgen_csr_aliasing	2.000s	40.452us	1	1	100.00
		pattgen_same_csr_outstanding	3.000s	12.613us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	pattgen_tl_intg_err	4.000s	91.844us	1	1	100.00
		pattgen_sec_cm	3.000s	80.598us	1	1	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	4.000s	91.844us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	1.517m	12.417ms	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	pattgen_inactive_level	4.000s	98.387us	1	1	100.00
		TOTAL			16	18	88.89

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:946) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

Test pattgen_stress_all_with_rand_reset has 1 failures.

0.pattgen_stress_all_with_rand_reset.95427628971506079075365017018919650379781073947513320982380837752190159344928
Line 122, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 959738316 ps: (cip_base_vseq.sv:946) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 959750141 ps: (cip_base_vseq.sv:850) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 959750141 ps: (cip_base_vseq.sv:853) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 1/10
  UVM_INFO @ 960068326 ps: (cip_base_vseq.sv:874) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: has 1 failures:
- Test pattgen_stress_all has 1 failures.
  - 0.pattgen_stress_all.96501844049900443362058777820044631186281977542062315099448932649699535209799
    Line 152, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all/latest/run.log
```
  UVM_ERROR @ 114701558 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
  ------------------------------------
  Name      Type          Size  Value
  ------------------------------------
  exp_item  pattgen_item  -     @10233
```